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* [mips] Fix sc, scs, ll, lld instructions expandingSimon Atanasyan2019-11-271-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a couple of bugs with the sc, scs, ll, lld instructions expanding: 1. On R6 these instruction pack immediate offset into a 9-bit field. Now if an immediate exceeds 9-bits assembler does not perform expansion and just rejects such instruction. 2. On 64-bit non-PIC code if an operand is a symbol assembler generates incorrect sequence of instructions. It uses R_MIPS_HI16 and R_MIPS_LO16 relocations and skips R_MIPS_HIGHEST and R_MIPS_HIGHER ones. To solve these problems this patch: - Introduces `mem_simm9_exp` to mark 9-bit memory immediate operands which require expansion. Probably later all `mem_simm9` operands will be able to migrate on `mem_simm9_exp` and we rename it to `mem_simm9`. - Adds new `OPERAND_MEM_SIMM9` operand type and assigns it to the `mem_simm9_exp`. That allows to know operand size in the `processInstruction` method and decide whether we need to expand instruction. - Adds `expandMem9Inst` method to expand instructions with 9-bit memory immediate operand. This method just load immediate into a "base" register used by origibal instruction: sc $2, 256($sp) => addiu $1, $sp, 256 sc $2, 0($1) - Fix `expandMem16Inst` to support a correct set of relocations for symbol loading in case of 64-bit non-PIC code. ll $12, symbol => lui $12, 0 R_MIPS_HIGHEST symbol daddiu $12, $12, 0 R_MIPS_HIGHER symbol dsll $12, $12, 16 daddiu $12, $12, 0 R_MIPS_HI16 symbol dsll $12, $12, 16 ll $12, 0($12) R_MIPS_LO16 symbol - Fix `expandMem16Inst` to unify handling of 3 and 4 operands instructions. - Delete unused now `MipsTargetStreamer::emitSCWithSymOffset` method. Task for next patches - implement expanding for other instructions use `mem_simm9` operand and other `mem_simm##` operands. Differential Revision: https://reviews.llvm.org/D70648
* [mips] Remove unused `IsPCRelativeLoad` MIPS instructions attribute. NFCSimon Atanasyan2019-11-211-4/+1
| | | | This attribute is always set to zero.
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [mips] Emit .reloc R_{MICRO}MIPS_JALR along with j(al)r(c) $25Vladimir Stefanovic2019-01-171-1/+4
| | | | | | | | | | | | The callee address is added as an optional operand (MCSymbol) in AdjustInstrPostInstrSelection() and then used by asm printer to insert: '.reloc tmplabel, R_MIPS_JALR, symbol tmplabel:'. Controlled with '-mips-jalr-reloc', default is true. Differential revision: https://reviews.llvm.org/D56694 llvm-svn: 351485
* [mips] Correct c.cond.fmt instruction definition.Simon Dardis2017-01-161-1/+3
| | | | | | | | | | | | | | | Permit explicit $fcc<X> operand in c.cond.fmt instruction. Add c.cond.fmt to the MIPS to microMIPS instruction mapping table. Check that $fcc1 - $fcc7 are unusable for MIPS-I to MIPS-III for c.cond.fmt, bc1t, bc1f. Reviewers: seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D24510 llvm-svn: 292117
* [mips][microMIPS] Implement DBITSWAP, DLSA and LWUPC and add tests for AUI ↵Hrvoje Varga2016-09-081-1/+4
| | | | | | | | instructions Differential Revision: https://reviews.llvm.org/D16452 llvm-svn: 280909
* [mips] Use MipsMCExpr instead of MCSymbolRefExpr for all relocations.Daniel Sanders2016-05-031-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is much closer to the way MIPS relocation expressions work (%hi(foo + 2) rather than %hi(foo) + 2) and removes the need for the various bodges in MipsAsmParser::evaluateRelocExpr(). Removing those bodges ensures that the constant stored in MCValue is the full 32 or 64-bit (depending on ABI) offset from the symbol. This will be used to correct the %hi/%lo matching needed to sort the relocation table correctly. As part of this: * Gave MCExpr::print() the ability to omit parenthesis when emitting a symbol reference inside a MipsMCExpr operator like %hi(X). Without this we print things like %lo(($L1)). * %hi(%neg(%gprel(X))) is now three MipsMCExpr's instead of one. Most of the related special cases have been removed or moved to MipsMCExpr. We can remove the rest as we gain support for the less common relocations when they are not part of this specific combination. * Renamed MipsMCExpr::VariantKind and the enum prefix ('VK_') to avoid confusion with MCSymbolRefExpr::VariantKind and its prefix (also 'VK_'). * fixup_Mips_GOT_Local and fixup_Mips_GOT_Global were found to be identical and merged into fixup_Mips_GOT. * MO_GOT16 and MO_GOT turned out to be identical and have been merged into MO_GOT. * VK_Mips_GOT and VK_Mips_GOT16 turned out to be the same thing so they have been merged into MEK_GOT Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19716 llvm-svn: 268379
* [mips] MIPS32R6 compact branch supportDaniel Sanders2016-03-141-1/+6
| | | | | | | | | | | | | | | | | | | | | | | Summary: MIPSR6 introduces a class of branches called compact branches. Unlike the traditional MIPS branches which have a delay slot, compact branches do not have a delay slot. The instruction following the compact branch is only executed if the branch is not taken and must not be a branch. It works by generating compact branches for MIPS32R6 when the delay slot filler cannot fill a delay slot. Then, inspecting the generated code for forbidden slot hazards (a compact branch with an adjacent branch or other CTI) and inserting nops to clear this hazard. Patch by Simon Dardis. Reviewers: vkalintiris, dsanders Subscribers: MatzeB, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16353 llvm-svn: 263444
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-2/+2
| | | | | | Apparently, the style needs to be agreed upon first. llvm-svn: 240390
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-2/+2
| | | | | | | | | | | | | The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! llvm-svn: 240137
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* Completely rewrite ELFObjectWriter::RecordRelocation.Rafael Espindola2014-03-291-28/+0
| | | | | | | | | | | | | | | | | | | I started trying to fix a small issue, but this code has seen a small fix too many. The old code was fairly convoluted. Some of the issues it had: * It failed to check if a symbol difference was in the some section when converting a relocation to pcrel. * It failed to check if the relocation was already pcrel. * The pcrel value computation was wrong in some cases (relocation-pc.s) * It was missing quiet a few cases where it should not convert symbol relocations to section relocations, leaving the backends to patch it up. * It would not propagate the fact that it had changed a relocation to pcrel, requiring a quiet nasty work around in ARM. * It was missing comments. llvm-svn: 205076
* [mips] Set HWEncoding field of registers. Use delete functionAkira Hatanaka2012-12-101-93/+0
| | | | | | getMipsRegisterNumbering and use MCRegisterInfo::getEncodingValue instead. llvm-svn: 169760
* [mips] Add target operand flag enums for big GOT relocations.Akira Hatanaka2012-11-211-1/+7
| | | | llvm-svn: 168450
* Add case clauses for returning dsp accumulator encoding values in functionAkira Hatanaka2012-09-261-2/+4
| | | | | | getMipsRegisterNumbering. llvm-svn: 164720
* The Mips standalone assembler fpu instruction support.Jack Carter2012-09-071-1/+1
| | | | | | | Test cases included Contributer: Vladimir Medic llvm-svn: 163363
* Add comment for relocations MO_HIGHER and HIGHEST in MipsBaseInfo.h.Akira Hatanaka2012-07-231-0/+2
| | | | llvm-svn: 160636
* Add HIGHER and HIGHEST relocations to Mips backend.Akira Hatanaka2012-07-211-1/+4
| | | | llvm-svn: 160599
* Define function MipsGetSymAndOffset which returns a fixup's symbol and theAkira Hatanaka2012-03-271-0/+30
| | | | | | offset applied to it. llvm-svn: 153493
* remove blanks, and some code formatJia Liu2012-02-281-1/+1
| | | | llvm-svn: 151625
* replace a balnk with -Jia Liu2012-02-241-1/+1
| | | | llvm-svn: 151337
* add Emacs tag and fix some comment error in file headersJia Liu2012-02-171-1/+1
| | | | llvm-svn: 150775
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-1/+0
| | | | llvm-svn: 148578
* Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct objectAkira Hatanaka2011-12-141-0/+7
| | | | | | | emission is not supported yet, but a patch that adds the support should follow soon. llvm-svn: 146572
* Add a few moreLocal/Global R_MIPS_GOT related fixups andBruno Cardoso Lopes2011-12-071-1/+2
| | | | | | | | make the addend fixup code a bit more generic Patch by Jack Carter. llvm-svn: 145998
* Add register HWR29 numbering. Patch by Jack CarterBruno Cardoso Lopes2011-12-061-0/+1
| | | | llvm-svn: 145910
* Mips MC object code emission improvements:Bruno Cardoso Lopes2011-11-111-0/+82
| | | | | | | | | | "With this patch we can now generate runnable Mips code through LLVM direct object emission. We have run numerous simple programs, both C and C++ and with -O0 and -O3 from the output. The code is not production ready, but quite useful for experimentation." Patch and message by Jack Carter llvm-svn: 144414
* Definition of function getMipsRegisterNumbering.Akira Hatanaka2011-10-141-0/+113
Patch by Jack Carter and Reed Kotler at Mips. llvm-svn: 141938
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