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* [Hexagon] Do not check alignment for unsized types in isLegalAddressingModeKrzysztof Parzyszek2016-08-031-7/+16
| | | | | | | | When the same base address is used to load two different data types, LSR would assume a memory type of "void". This type is not sized and has no alignment information. Checking for it causes a crash. llvm-svn: 277601
* [Hexagon] Recognize vcombine in copy propagationKrzysztof Parzyszek2016-08-021-2/+8
| | | | llvm-svn: 277528
* [Hexagon] Prefer _io over _rr for 64-bit store with constant offsetKrzysztof Parzyszek2016-08-021-0/+13
| | | | | | | | | Identify patterns where the address is aligned to an 8-byte boundary, but both the base address and the constant offset are both proper multiples of 4. In such cases, extract Base+4 into a separate instruc- tion, and use S2_storerd_io, instead of using S4_storerd_rr. llvm-svn: 277497
* [Hexagon] Remove unused optionKrzysztof Parzyszek2016-08-021-7/+0
| | | | llvm-svn: 277496
* [Hexagon] Improvements to address mode checks in TargetLoweringKrzysztof Parzyszek2016-08-022-2/+39
| | | | | | | - Implement getOptimalMemOpType. - Check BaseOffset in isLegalAddressingMode. llvm-svn: 277494
* HexagonVectorPrint.cpp: Fix r277370. Don't use getInstrVecReg() in the ↵NAKAMURA Takumi2016-08-021-1/+2
| | | | | | expression of assert(). It has side effects. llvm-svn: 277448
* [Hexagon] Tidy up some code, NFC: reapply r277372 with a fixKrzysztof Parzyszek2016-08-012-192/+175
| | | | llvm-svn: 277383
* Revert r277372, it is causing buildbot failuresKrzysztof Parzyszek2016-08-012-173/+186
| | | | llvm-svn: 277374
* [Hexagon] Tidy up some code, NFCKrzysztof Parzyszek2016-08-012-186/+173
| | | | llvm-svn: 277372
* [Hexagon] Generate vector printing instructionsRon Lieberman2016-08-013-0/+188
| | | | llvm-svn: 277370
* Replace MachineInstr* with MachineInstr& in TargetInstrInfo, NFCKrzysztof Parzyszek2016-08-015-31/+31
| | | | | | There were a few cases introduced with the modulo scheduler. llvm-svn: 277358
* [Hexagon] Check for offset overflow when reserving scavenging slotsKrzysztof Parzyszek2016-08-012-2/+16
| | | | | | | | | Scavenging slots were only reserved when pseudo-instruction expansion in frame lowering created new virtual registers. It is possible to still need a scavenging slot even if no virtual registers were created, in cases where the stack is large enough to overflow instruction offsets. llvm-svn: 277355
* [HexagonConstPropagation] Remove dead code.Davide Italiano2016-07-301-22/+0
| | | | llvm-svn: 277285
* [HexagonBitSimplify] Remove dead code.Davide Italiano2016-07-301-18/+0
| | | | llvm-svn: 277284
* [Hexagon] Perform bit arithmetic on unsigned to avoid accidentally shifting ↵Benjamin Kramer2016-07-301-2/+2
| | | | | | | | negative values. Found by ubsan. llvm-svn: 277268
* [Hexagon] Referencify MachineInstr in HexagonInstrInfo, NFCKrzysztof Parzyszek2016-07-2915-808/+787
| | | | llvm-svn: 277220
* Fixed MSVC out of range shift warningSimon Pilgrim2016-07-291-1/+1
| | | | llvm-svn: 277195
* Revert r277178, the actual change had already been appliedKrzysztof Parzyszek2016-07-291-0/+1
| | | | | | Will submit another patch with the testcase only. llvm-svn: 277180
* [Hexagon] Misaligned loads and stores are not fastKrzysztof Parzyszek2016-07-291-1/+0
| | | | | | | | | | | | The DAG combiner tries to merge stores to adjacent vector wide memory locations by creating stores which are integral multiples of the vector width. Discourage this by informing it that this is slow. This should not affect legalization passes, because all of them ignore the "Fast" argument. Patch by Pranav Bhandarkar. llvm-svn: 277178
* MachinePipeliner pass that implements Swing Modulo SchedulingBrendon Cahoon2016-07-293-4/+139
| | | | | | | | | | | | | | | | | | | | | | | | Software pipelining is an optimization for improving ILP by overlapping loop iterations. Swing Modulo Scheduling (SMS) is an implementation of software pipelining that attempts to reduce register pressure and generate efficient pipelines with a low compile-time cost. This implementaion of SMS is a target-independent back-end pass. When enabled, the pass should run just prior to the register allocation pass, while the machine IR is in SSA form. If the pass is successful, then the original loop is replaced by the optimized loop. The optimized loop contains one or more prolog blocks, the pipelined kernel, and one or more epilog blocks. This pass is enabled for Hexagon only. To enable for other targets, a couple of target specific hooks must be implemented, and the pass needs to be called from the target's TargetMachine implementation. Differential Review: http://reviews.llvm.org/D16829 llvm-svn: 277169
* [Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVXKrzysztof Parzyszek2016-07-293-22/+199
| | | | | | | | | | | | | | | | If the mask of a vector shuffle has alternating odd or even numbers starting with 1 or 0 respectively up to the largest possible index for the given type in the given HVX mode (single of double) we can generate vpacko or vpacke instruction respectively. E.g. %42 = shufflevector <32 x i16> %37, <32 x i16> %41, <32 x i32> <i32 1, i32 3, ..., i32 63> is %42.h = vpacko(%41.w, %37.w) Patch by Pranav Bhandarkar. llvm-svn: 277168
* [Hexagon] Improve balancing of address calculationKrzysztof Parzyszek2016-07-291-3/+738
| | | | | | | | | Rebalances address calculation trees and applies Hexagon-specific optimizations to the trees to improve instruction selection. Patch by Tobias Edler von Koch. llvm-svn: 277151
* Fix license information in the file headerKrzysztof Parzyszek2016-07-291-2/+5
| | | | llvm-svn: 277145
* Add missing files to r277143Krzysztof Parzyszek2016-07-292-0/+213
| | | | llvm-svn: 277144
* [Hexagon] Implement DFA based hazard recognizerKrzysztof Parzyszek2016-07-292-3/+11
| | | | | | | | | | | The post register allocator scheduler can generate poor schedules because the scoreboard hazard recognizer is unable to identify hazards for Hexagon precisely. Instead, Hexagon should use a DFA based hazard recognizer. Patch by Brendon Cahoon. llvm-svn: 277143
* Fixed MSVC out of range shift warningSimon Pilgrim2016-07-291-1/+1
| | | | llvm-svn: 277130
* Fix build breaks after r277028Krzysztof Parzyszek2016-07-281-0/+1
| | | | llvm-svn: 277031
* [Hexagon] Implement MI-level constant propagationKrzysztof Parzyszek2016-07-283-0/+3218
| | | | llvm-svn: 277028
* [Hexagon] Insert CFI instructions before throwing callsKrzysztof Parzyszek2016-07-281-20/+31
| | | | | | | | Normally, CFI instructions should be inserted after allocframe, but if allocframe is in the same packet with a call, the CFI instructions should be inserted before that packet. llvm-svn: 277020
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-286-68/+68
| | | | | | | getFrameInfo() never returns nullptr so we should use a reference instead of a pointer. llvm-svn: 277017
* [Hexagon] Find speculative loop preheader in hardware loop generationKrzysztof Parzyszek2016-07-271-10/+57
| | | | | | | | Before adding a new preheader block, check if there is a candidate block where the loop setup could be placed speculatively. This will be off by default. llvm-svn: 276919
* [Hexagon] Add option to bisect spill slot optimizationKrzysztof Parzyszek2016-07-271-2/+17
| | | | llvm-svn: 276917
* [Hexagon] Do not optimize volatile stack spill slotsKrzysztof Parzyszek2016-07-271-22/+11
| | | | llvm-svn: 276916
* [Hexagon] Handle extended versions of restore routinesKrzysztof Parzyszek2016-07-271-2/+11
| | | | llvm-svn: 276903
* [Hexagon] Add saved callee-saved registers as live-in in non-wrapped blocksKrzysztof Parzyszek2016-07-272-8/+28
| | | | | | | | | | | | | The callee-saved registers that are saved in a function are not pristine, and so they can be defined and used. In case of shrink-wrapping though, there are blocks that are outside of the save/restore range, and in those blocks the saved registers must be treated as pristine. To avoid any uses of these registers, add them as live-in in all those blocks. This was already done for blocks reaching function exits after restore, add code that does the same for blocks reached from the function entry before save. llvm-svn: 276886
* [Hexagon] Post-increment loads/stores enhancementsKrzysztof Parzyszek2016-07-265-112/+99
| | | | | | | - Generate vector post-increment stores more aggressively. - Predicate post-increment and vector stores in early if-conversion. llvm-svn: 276800
* [Hexagon] Gracefully handle reg class mismatch in HexagonLoopRescheduleKrzysztof Parzyszek2016-07-261-13/+19
| | | | llvm-svn: 276793
* [Hexagon] Rerun bit tracker on new instructions in RIEKrzysztof Parzyszek2016-07-263-5/+17
| | | | | | | | | | | | | | | | | | | Consider this case: vreg1 = A2_zxth vreg0 (1) ... vreg2 = A2_zxth vreg1 (2) Redundant instruction elimination could delete the instruction (1) because the user (2) only cares about the low 16 bits. Then it could delete (2) because the input is already zero-extended. The problem is that the properties allowing each individual instruction to be deleted depend on the existence of the other instruction, so either one can be deleted, but not both. The existing check for this situation in RIE was insufficient. The fix is to update all dependent cells when an instruction is removed (replaced via COPY) in RIE. llvm-svn: 276792
* [Hexagon] Bitwise operations for insert/extract word not simplifiedKrzysztof Parzyszek2016-07-262-25/+85
| | | | | | | Change the bit simplifier to generate REG_SEQUENCE instructions in addition to COPY, which will handle cases of word insert/extract. llvm-svn: 276787
* [Hexagon] Add support for proper handling of H and L constraintsKrzysztof Parzyszek2016-07-261-8/+16
| | | | | | | | | H -> High part of reg pair. L -> Low part of reg pair. Patch by Sundeep Kushwaha. llvm-svn: 276773
* [Hexagon] Update store offset when not packetizing it with allocframeKrzysztof Parzyszek2016-07-262-15/+51
| | | | | | | | | | When the packetizer wants to put a store to a stack slot in the same packet with an allocframe, it updates the store offset to reflect the value of SP before it is updated by allocframe. If the store cannot be packetized with the allocframe after all, the offset needs to be updated back to the previous value. llvm-svn: 276749
* MC] Provide an MCTargetOptions to implementors of MCAsmBackendCtorTy, NFCJoel Jones2016-07-252-2/+5
| | | | | | | | | | | | | | | Some targets, notably AArch64 for ILP32, have different relocation encodings based upon the ABI. This is an enabling change, so a future patch can use the ABIName from MCTargetOptions to chose which relocations to use. Tested using check-llvm. The corresponding change to clang is in: http://reviews.llvm.org/D16538 Patch by: Joel Jones Differential Revision: https://reviews.llvm.org/D16213 llvm-svn: 276654
* [Hexagon] Add target feature to generate long callsKrzysztof Parzyszek2016-07-256-29/+73
| | | | llvm-svn: 276638
* [Hexagon] Make HexagonCodeGen depend on ScalarKrzysztof Parzyszek2016-07-221-12/+13
| | | | | | Hexagon backend uses LoopDataPrefetch pass that is defined in Scalar. llvm-svn: 276441
* [RDF] Make the graph construction/use less expensiveKrzysztof Parzyszek2016-07-222-7/+23
| | | | | | | | | - FuncNode::findBlock traverses the function every time. Avoid using it, and keep a cache of block addresses in DataFlowGraph instead. - The operator[] in the map of definition stacks was very slow. Replace the map with unordered_map. llvm-svn: 276429
* [Hexagon] Use loop data prefetch on HexagonKrzysztof Parzyszek2016-07-225-0/+29
| | | | llvm-svn: 276422
* [Hexagon] Handle returning small structures by valueKrzysztof Parzyszek2016-07-181-1/+7
| | | | | | | This is not compliant with the official ABI, but allows experimentation with calling conventions. llvm-svn: 275825
* [Hexagon] Revert r275822: mistake in commit messageKrzysztof Parzyszek2016-07-181-7/+1
| | | | llvm-svn: 275824
* [Hexagon] Handle returning small structures by valueKrzysztof Parzyszek2016-07-181-1/+7
| | | | | | | This is compliant with the official ABI, but allows experimentation with calling conventions. llvm-svn: 275822
* [Hexagon] Misc changes to HexagonMachineScheduler, NFCKrzysztof Parzyszek2016-07-181-26/+3
| | | | | | | - Remove duplicated code. - Convert loop to range-for. llvm-svn: 275806
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