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* TableGen: Check scheduling models for completenessMatthias Braun2016-03-013-0/+3
| | | | | | | | | | | | | | | | | | | | | | TableGen checks at compiletime that for scheduling models with "CompleteModel = 1" one of the following holds: - Is marked with the hasNoSchedulingInfo flag - The instruction is a subclass of Sched - There are InstRW definitions in the scheduling model Typical steps necessary to complete a model: - Ensure all pseudo instructions that are expanded before machine scheduling (usually everything handled with EmitYYY() functions in XXXTargetLowering). - If a CPU does not support some instructions mark the corresponding resource unsupported: "WriteRes<WriteXXX, []> { let Unsupported = 1; }". - Add missing scheduling information. Differential Revision: http://reviews.llvm.org/D17747 llvm-svn: 262384
* [Hexagon] As a size optimization, not lazy extending TPREL or DTPREL ↵Colin LeMahieu2016-02-291-8/+14
| | | | | | variants since they're usually in range. llvm-svn: 262258
* [Hexagon] Missed member initialization causing ubsan failure.Colin LeMahieu2016-02-291-1/+2
| | | | llvm-svn: 262252
* [Hexagon] Setting sign mismatch flag on expression instead of using bit tricks.Colin LeMahieu2016-02-293-16/+22
| | | | llvm-svn: 262243
* [Hexagon] Using MustExtend flag on expression instead of passing around bools.Colin LeMahieu2016-02-294-55/+64
| | | | llvm-svn: 262238
* CodeGen: Change MachineInstr to use MachineInstr&, NFCDuncan P. N. Exon Smith2016-02-271-2/+2
| | | | | | | | Change MachineInstr API to prefer MachineInstr& over MachineInstr* whenever the parameter is expected to be non-null. Slowly inching toward being able to fix PR26753. llvm-svn: 262149
* CodeGen: Update DFAPacketizer API to take MachineInstr&, NFCDuncan P. N. Exon Smith2016-02-273-40/+40
| | | | | | | | | In all but one case, change the DFAPacketizer API to take MachineInstr& instead of MachineInstr*. In DFAPacketizer::endPacket(), take MachineBasicBlock::iterator. Besides cleaning up the API, this is in search of PR26753. llvm-svn: 262142
* WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFCDuncan P. N. Exon Smith2016-02-275-9/+9
| | | | | | | | Update APIs in MachineInstrBundle.h to take and return MachineInstr& instead of MachineInstr* when the instruction cannot be null. Besides being a nice cleanup, this is tacking toward a fix for PR26753. llvm-svn: 262141
* CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFCDuncan P. N. Exon Smith2016-02-271-5/+5
| | | | | | | | | | | | | | Take MachineInstr by reference instead of by pointer in SlotIndexes and the SlotIndex wrappers in LiveIntervals. The MachineInstrs here are never null, so this cleans up the API a bit. It also incidentally removes a few implicit conversions from MachineInstrBundleIterator to MachineInstr* (see PR26753). At a couple of call sites it was convenient to convert to a range-based for loop over MachineBasicBlock::instr_begin/instr_end, so I added MachineBasicBlock::instrs. llvm-svn: 262115
* Introduce analysis pass to compute PostDominators in the new pass manager. NFCHongbin Zheng2016-02-251-4/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D17537 llvm-svn: 261902
* CodeGen: TII: Take MachineInstr& in predicate API, NFCDuncan P. N. Exon Smith2016-02-2311-105/+100
| | | | | | | | | | | | | Change TargetInstrInfo API to take `MachineInstr&` instead of `MachineInstr*` in the functions related to predicated instructions (I'll try to come back later and get some of the rest). All of these functions require non-null parameters already, so references are more clear. As a bonus, this happens to factor away a host of implicit iterator => pointer conversions. No functionality change intended. llvm-svn: 261605
* CodeGen: Bring back MachineBasicBlock::iterator::getInstrIterator()...Duncan P. N. Exon Smith2016-02-223-4/+4
| | | | | | | | | | | | | | | | | | This is a little embarrassing. When I reverted r261504 (getIterator() => getInstrIterator()) in r261567, I did a `git grep` to see if there were new calls to `getInstrIterator()` that I needed to migrate. There were 10-20 hits, and I blindly did a `sed ...` before calling `ninja check`. However, these were `MachineInstrBundleIterator::getInstrIterator()`, which predated r261567. Perhaps coincidentally, these had an identical name and return type. This commit undoes my careless sed and restores `MachineBasicBlock::iterator::getInstrIterator()`. llvm-svn: 261577
* Revert "CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC"Duncan P. N. Exon Smith2016-02-225-9/+9
| | | | | | | | | | This reverts commit r261504, since it's not obvious the new name is better: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20160222/334298.html I'll recommit if we get consensus that it's the right direction. llvm-svn: 261567
* CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFCDuncan P. N. Exon Smith2016-02-213-5/+5
| | | | | | | | | | | | | | | | | | | | | | | Delete MachineInstr::getIterator(), since the term "iterator" is overloaded when talking about MachineInstr. - Downcast to ilist_node in iplist::getNextNode() and getPrevNode() so that ilist_node::getIterator() is still available. - Add it back as MachineInstr::getInstrIterator(). This matches the naming in MachineBasicBlock. - Add MachineInstr::getBundleIterator(). This is explicitly called "bundle" (not matching MachineBasicBlock) to disintinguish it clearly from ilist_node::getIterator(). - Update all calls. Some of these I switched to `auto` to remove boiler-plate, since the new name is clear about the type. There was one call I updated that looked fishy, but it wasn't clear what the right answer was. This was in X86FrameLowering::inlineStackProbe(), added in r252578 in lib/Target/X86/X86FrameLowering.cpp. I opted to leave the behaviour unchanged, but I'll reply to the original commit on the list in a moment. llvm-svn: 261504
* [Hexagon] Remove redundant check.Chad Rosier2016-02-181-2/+2
| | | | llvm-svn: 261232
* [Hexagon] Fix compilation error with GCC 6Krzysztof Parzyszek2016-02-181-66/+68
| | | | | | | | | | | | | | Compiling Hexagon target with GCC 6 produces "error: should have been declared inside" due to GCC PR c++/69657 which was merged. Properly wrapping operator<<() definitions within the namespace llvm fixes the issue. Author: domagoj.stolfa Differential Revision: http://reviews.llvm.org/D17281 llvm-svn: 261220
* [Hexagon] Implement TLS supportKrzysztof Parzyszek2016-02-185-2/+202
| | | | | | Patch by Anand Kodnani. llvm-svn: 261218
* [Hexagon] Add support for __builtin_prefetchKrzysztof Parzyszek2016-02-183-0/+38
| | | | llvm-svn: 261210
* [Hexagon] Update the callee-saved register set for EH-aware functionsKrzysztof Parzyszek2016-02-181-3/+15
| | | | llvm-svn: 261208
* [Hexagon] Replacing reference/dereference with reference cast.Colin LeMahieu2016-02-171-4/+4
| | | | llvm-svn: 261133
* [Hexagon] Loop instructions don't need special processing. Extension and ↵Colin LeMahieu2016-02-171-25/+0
| | | | | | fitting is performed by generic code and the comment is incorrect, loops don't have a separate extended opcode. llvm-svn: 261118
* [Hexagon] Fold object construction into map::insertKrzysztof Parzyszek2016-02-171-2/+2
| | | | llvm-svn: 261096
* [Hexagon] cast<> a reference instead of referencing + dereferencing.Benjamin Kramer2016-02-171-1/+1
| | | | llvm-svn: 261077
* [Hexagon] Adding relocation for code size, cold path optimization allowing a ↵Colin LeMahieu2016-02-1611-1/+70
| | | | | | | | | | | | 23-bit 4-byte aligned relocation to be a valid instruction encoding. The usual way to get a 32-bit relocation is to use a constant extender which doubles the size of the instruction, 4 bytes to 8 bytes. Another way is to put a .word32 and mix code and data within a function. The disadvantage is it's not a valid instruction encoding and jumping over it causes prefetch stalls inside the hardware. This relocation packs a 23-bit value in to an "r0 = add(rX, #a)" instruction by overwriting the source register bits. Since r0 is the return value register, if this instruction is placed after a function call which return void, r0 will be filled with an undefined value, the prefetch won't be confused, and the callee can access the constant value by way of the link register. llvm-svn: 261006
* [Hexagon] Hoist nonnull assert up.Benjamin Kramer2016-02-162-1/+1
| | | | | | | | Once a pointer is turned into a reference it cannot be nullptr, clang rightfully warns about this assert being a tautology. Put the assert before the reference is created. llvm-svn: 260949
* [NFC] Fixing naming convention, lowercase start of function name.Colin LeMahieu2016-02-156-33/+33
| | | | llvm-svn: 260903
* [Hexagon] Wrapping all MCExprs inside MCOperands within HexagonMCExpr to ↵Colin LeMahieu2016-02-158-92/+169
| | | | | | simplify handling and allow flags on the expression. llvm-svn: 260902
* [Hexagon] Use zero-extending loads for anyextKrzysztof Parzyszek2016-02-151-6/+6
| | | | llvm-svn: 260895
* [Hexagon] Replace use of "std::map::emplace" with "insert"Krzysztof Parzyszek2016-02-131-1/+4
| | | | | | | Gcc 4.7.2-4 does not seem to have "emplace" in its implementation of map. This should fix the build failure on polly-amd64-linux. llvm-svn: 260816
* HexagonFrameLowering.cpp: Appease msc18 to give an explicit constructor ↵NAKAMURA Takumi2016-02-131-2/+4
| | | | | | SlotInfo() instead of member initializers. llvm-svn: 260812
* Fix Windows buildbot breakage.Alexey Samsonov2016-02-121-3/+4
| | | | llvm-svn: 260766
* [Hexagon] Optimize stack slot spillsKrzysztof Parzyszek2016-02-125-3/+1089
| | | | | | | | | | | | | | Replace spills to memory with spills to registers, if possible. This applies mostly to predicate registers (both scalar and vector), since they are very limited in number. A spill of a predicate register may happen even if there is a general-purpose register available. In cases like this the stack spill/reload may be eliminated completely. This optimization will consider all stack objects, regardless of where they came from and try to match the live range of the stack slot with a dead range of a register from an appropriate register class. llvm-svn: 260758
* [Hexagon] Mark HVX registers as volatileKrzysztof Parzyszek2016-02-121-1/+7
| | | | llvm-svn: 260753
* [Hexagon] Recognize more cases in copyPhysReg and stack slot load/storeKrzysztof Parzyszek2016-02-121-51/+105
| | | | llvm-svn: 260748
* [Hexagon] Recognize more instructions in isLoadFromStackSlot/isStoreToStackSlotKrzysztof Parzyszek2016-02-121-19/+99
| | | | llvm-svn: 260725
* [Hexagon] Add utility functions to detect sign- and zero-extending loadsKrzysztof Parzyszek2016-02-122-1/+161
| | | | llvm-svn: 260698
* [Hexagon] Replace expansion of spill pseudo-instructions in frame loweringKrzysztof Parzyszek2016-02-122-320/+475
| | | | | | | | | Rewrite the code to handle all pseudo-instructions in a single pass. This temporarily reverts spill slot optimization that used general- purpose registers to hold values of spilled predicate registers. llvm-svn: 260696
* [Hexagon] Remove HexagonExpandPredSpillCode passKrzysztof Parzyszek2016-02-123-203/+0
| | | | | | This code is dead. The expansion is now done in HexagonFrameLowering. llvm-svn: 260691
* [Hexagon] Eliminate pseudo instructions for circ/brev loads and storesKrzysztof Parzyszek2016-02-125-461/+192
| | | | | | | | | We can generate the actual instructions from the intrinsics without the need for pseudo-instructions. Also, since the intrinsics have a side- effect in a form of a store, attempt to optimize away loads from the store location. llvm-svn: 260690
* [Hexagon] Handle out-of-range offsets in eliminateFrameIndexKrzysztof Parzyszek2016-02-121-12/+15
| | | | | | | Create a virtual register that will hold the actual address and use it with the offset of 0 in the place of the original FI. llvm-svn: 260688
* [Hexagon] Specify vector alignment in DataLayout stringKrzysztof Parzyszek2016-02-121-7/+7
| | | | | | | | | | | The DataLayout can calculate alignment of vectors based on the alignment of the element type and the number of elements. In fact, it is the product of these two values. The problem is that for vectors of N x i1, this will return the alignment of N bytes, since the alignment of i1 is 8 bits. The vector types of vNi1 should be aligned to N bits instead. Provide explicit alignment for HVX vectors to avoid such complications. llvm-svn: 260678
* [MC] Merge VK_PPC_TPREL in to generic VK_TPREL.Colin LeMahieu2016-02-102-21/+21
| | | | | | Differential Revision: http://reviews.llvm.org/D17038 llvm-svn: 260401
* [Hexagon] Fixing relocation generation and adding tests.Colin LeMahieu2016-02-092-182/+263
| | | | llvm-svn: 260259
* Move classes defined in a cpp file into an anonymous namespace.Benjamin Kramer2016-02-051-0/+2
| | | | | | No functionality change intended. llvm-svn: 259883
* [NFC] Referencing manual for reason why subregbit is checkedColin LeMahieu2016-02-011-1/+2
| | | | llvm-svn: 259380
* Replace usages of llvm::utostr_32 with just llvm::utostr. While this is less ↵Craig Topper2016-01-311-20/+20
| | | | | | efficient, its unclear the few places that were using the _32 version were doing so for efficiency. llvm-svn: 259330
* Rename TargetSelectionDAGInfo into SelectionDAGTargetInfo and move it to ↵Benjamin Kramer2016-01-271-3/+3
| | | | | | | | CodeGen/ It's a SelectionDAG thing, not a Target thing. llvm-svn: 258939
* Move MCTargetAsmParser.h to llvm/MC/MCParser where it belongs.Benjamin Kramer2016-01-271-5/+5
| | | | llvm-svn: 258917
* Remove autoconf supportChris Bieneman2016-01-265-88/+0
| | | | | | | | | | | | | | | | Summary: This patch is provided in preparation for removing autoconf on 1/26. The proposal to remove autoconf on 1/26 was discussed on the llvm-dev thread here: http://lists.llvm.org/pipermail/llvm-dev/2016-January/093875.html "I felt a great disturbance in the [build system], as if millions of [makefiles] suddenly cried out in terror and were suddenly silenced. I fear something [amazing] has happened." - Obi Wan Kenobi Reviewers: chandlerc, grosbach, bob.wilson, tstellarAMD, echristo, whitequark Subscribers: chfast, simoncook, emaste, jholewinski, tberghammer, jfb, danalbert, srhines, arsenm, dschuff, jyknight, dsanders, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D16471 llvm-svn: 258861
* Reflect the MC/MCDisassembler split on the include/ level.Benjamin Kramer2016-01-261-1/+1
| | | | | | No functional change, just moving code around. llvm-svn: 258818
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