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authorDuncan P. N. Exon Smith <dexonsmith@apple.com>2016-02-27 20:01:33 +0000
committerDuncan P. N. Exon Smith <dexonsmith@apple.com>2016-02-27 20:01:33 +0000
commitfd8cc23220d25dfe6956470da8bd63d26649c428 (patch)
tree121ce8d85170b862228e2a15d45da0bc7ad8b68b /llvm/lib/Target/Hexagon
parent982224cfb8de39337e977219b3571c5a87aca4ce (diff)
downloadbcm5719-llvm-fd8cc23220d25dfe6956470da8bd63d26649c428.tar.gz
bcm5719-llvm-fd8cc23220d25dfe6956470da8bd63d26649c428.zip
CodeGen: Change MachineInstr to use MachineInstr&, NFC
Change MachineInstr API to prefer MachineInstr& over MachineInstr* whenever the parameter is expected to be non-null. Slowly inching toward being able to fix PR26753. llvm-svn: 262149
Diffstat (limited to 'llvm/lib/Target/Hexagon')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index 34dddb1132b..8bbc2e0c9b3 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -572,7 +572,7 @@ void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const {
unsigned NewOpc = Hexagon::L4_return;
MachineInstr *NewI = BuildMI(MBB, RetI, DL, HII.get(NewOpc));
// Transfer the function live-out registers.
- NewI->copyImplicitOps(MF, RetI);
+ NewI->copyImplicitOps(MF, *RetI);
MBB.erase(RetI);
}
@@ -983,7 +983,7 @@ bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB,
DeallocCall = BuildMI(MBB, It, DL, HII.get(ROpc))
.addExternalSymbol(RestoreFn);
// Transfer the function live-out registers.
- DeallocCall->copyImplicitOps(MF, It);
+ DeallocCall->copyImplicitOps(MF, *It);
}
addCalleeSaveRegistersAsImpOperand(DeallocCall, MaxR, true);
return true;
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