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* [SelectionDAG] Allow targets to specify legality of extloads' resultAhmed Bougacha2015-01-081-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | type (in addition to the memory type). The *LoadExt* legalization handling used to only have one type, the memory type. This forced users to assume that as long as the extload for the memory type was declared legal, and the result type was legal, the whole extload was legal. However, this isn't always the case. For instance, on X86, with AVX, this is legal: v4i32 load, zext from v4i8 but this isn't: v4i64 load, zext from v4i8 Whereas v4i64 is (arguably) legal, even without AVX2. Note that the same thing was done a while ago for truncstores (r46140), but I assume no one needed it yet for extloads, so here we go. Calls to getLoadExtAction were changed to add the value type, found manually in the surrounding code. Calls to setLoadExtAction were mechanically changed, by wrapping the call in a loop, to match previous behavior. The loop iterates over the MVT subrange corresponding to the memory type (FP vectors, etc...). I also pulled neighboring setTruncStoreActions into some of the loops; those shouldn't make a difference, as the additional types are illegal. (e.g., i128->i1 truncstores on PPC.) No functional change intended. Differential Revision: http://reviews.llvm.org/D6532 llvm-svn: 225421
* [Hexagon] Fix 225372 USR register is not fully complete. Removing Uses = ↵Colin LeMahieu2015-01-071-12/+12
| | | | | | [USR] maintains existing functionality to old instructions without encodings. llvm-svn: 225377
* [Hexagon] Adding floating point classification and creation.Colin LeMahieu2015-01-071-0/+45
| | | | llvm-svn: 225374
* [Hexagon] Adding encodings for v5 floating point instructions.Colin LeMahieu2015-01-071-0/+326
| | | | llvm-svn: 225372
* [Hexagon] Adding encoding for popcount, fastcorner, dword asr with rounding.Colin LeMahieu2015-01-072-1/+62
| | | | llvm-svn: 225371
* [Hexagon] Adding compound jump encodings.Colin LeMahieu2015-01-062-0/+266
| | | | llvm-svn: 225291
* [Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, ↵Colin LeMahieu2015-01-063-1/+101
| | | | | | dcfetch. llvm-svn: 225283
* [Hexagon] Adding encoding information for absolute address loads.Colin LeMahieu2015-01-061-124/+186
| | | | llvm-svn: 225279
* [Hexagon] Fix 225267. GP register is not yet fully implemented. Removing ↵Colin LeMahieu2015-01-061-2/+2
| | | | | | Uses [GP] maintains existing behavior. llvm-svn: 225270
* [Hexagon] Adding dealloc_return encoding and absolute address stores.Colin LeMahieu2015-01-065-239/+347
| | | | llvm-svn: 225267
* [Hexagon] Adding add/sub with carry, logical shift left by immediate and ↵Colin LeMahieu2015-01-052-226/+124
| | | | | | memop instructions. Removing old defs without bits and updating references. llvm-svn: 225210
* [Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and ↵Colin LeMahieu2015-01-051-57/+170
| | | | | | accumulating shifts. llvm-svn: 225201
* [Hexagon] Adding V4 bit manipulating instructions, removing ALU defs without ↵Colin LeMahieu2015-01-051-251/+104
| | | | | | encoding bits. llvm-svn: 225199
* [Hexagon] Adding V4 logic-logic instructions and tests.Colin LeMahieu2015-01-051-0/+55
| | | | llvm-svn: 225198
* [Hexagon] Adding orand, bitsplit reg/reg, and modwrap instructions.Colin LeMahieu2015-01-051-0/+57
| | | | llvm-svn: 225197
* [Hexagon] Adding round reg/imm and bitsplit instructions.Colin LeMahieu2015-01-052-0/+21
| | | | llvm-svn: 225188
* Replace several 'assert(false' with 'llvm_unreachable' or fold a condition ↵Craig Topper2015-01-051-1/+1
| | | | | | into the assert. llvm-svn: 225160
* Reverting 225045 and 225043 and XFAIL multiline.ll on hexagonColin LeMahieu2014-12-311-1/+1
| | | | llvm-svn: 225047
* [Hexagon] Removing assertion to appease buildbot until I can reproduce the ↵Colin LeMahieu2014-12-311-1/+0
| | | | | | problem llvm-svn: 225045
* [Hexagon] Changing an llvm_unreachable to an assertion and returning 0. ↵Colin LeMahieu2014-12-311-1/+2
| | | | | | Relocations aren't implemented yet but we don't need to abort for this in release builds. llvm-svn: 225043
* [Hexagon] Adding accumulating add/sub, doubleword logic-not variants, ↵Colin LeMahieu2014-12-311-0/+111
| | | | | | doubleword bitfield extract, word parity, accumulating multiplies with saturation. llvm-svn: 225024
* [Hexagon] Adding double-logic on predicate instructions.Colin LeMahieu2014-12-301-0/+60
| | | | llvm-svn: 225018
* [Hexagon] Adding newvalue compare and jumps.Colin LeMahieu2014-12-301-17/+35
| | | | llvm-svn: 225015
* [Hexagon] Adding postincrement register newvalue stores.Colin LeMahieu2014-12-301-0/+30
| | | | llvm-svn: 225010
* [Hexagon] Removing old newvalue store variants. Adding postincrement ↵Colin LeMahieu2014-12-302-96/+90
| | | | | | immediate newvalue stores. llvm-svn: 225009
* [Hexagon] Adding indexed store new-value variants.Colin LeMahieu2014-12-302-45/+100
| | | | llvm-svn: 225007
* [Hexagon] Adding indexed store of immediates.Colin LeMahieu2014-12-302-48/+97
| | | | llvm-svn: 225006
* [Hexagon] Adding indexed stores.Colin LeMahieu2014-12-302-81/+167
| | | | llvm-svn: 225005
* [Hexagon] Adding reg-reg indexed load forms.Colin LeMahieu2014-12-303-85/+135
| | | | llvm-svn: 224997
* [Hexagon] Dropping old combine instructions without encodings.Colin LeMahieu2014-12-303-79/+68
| | | | llvm-svn: 224992
* [Hexagon] Adding compare byte/halfword reg-reg/reg-imm forms. Adding ↵Colin LeMahieu2014-12-301-55/+121
| | | | | | compare to general register reg-imm form. llvm-svn: 224991
* [Hexagon] Updating constant extender def, adding alu-not instructions, ↵Colin LeMahieu2014-12-302-10/+43
| | | | | | compare to general register, and inverted compares. llvm-svn: 224989
* [Hexagon] Adding allocframe, post-increment circular immediate stores, ↵Colin LeMahieu2014-12-293-17/+149
| | | | | | post-increment circular register stores, and bit reversed post-increment stores. llvm-svn: 224957
* [Hexagon] Fixing 224952 where an addressing mode update was missed.Colin LeMahieu2014-12-291-1/+1
| | | | llvm-svn: 224955
* [Hexagon] Adding post-increment register form stores and register-immediate ↵Colin LeMahieu2014-12-296-180/+194
| | | | | | form stores with tests. llvm-svn: 224952
* [Hexagon] Replacing the remaining postincrement stores with versions that ↵Colin LeMahieu2014-12-293-58/+20
| | | | | | have encoding bits. llvm-svn: 224951
* [Hexagon] Renaming old multiclass for removal. Adding post-increment store ↵Colin LeMahieu2014-12-293-9/+104
| | | | | | classes and instruction defs. llvm-svn: 224949
* [Hexagon] Adding auto-incrementing loads with and without byte reversal.Colin LeMahieu2014-12-261-0/+76
| | | | llvm-svn: 224871
* [Hexagon] Adding locked loads.Colin LeMahieu2014-12-261-0/+19
| | | | llvm-svn: 224870
* [Hexagon] Adding deallocframe and circular addressing loads.Colin LeMahieu2014-12-265-8/+124
| | | | llvm-svn: 224869
* [Hexagon] Adding remaining post-increment instruction variants. Removing ↵Colin LeMahieu2014-12-263-61/+25
| | | | | | unused classes. llvm-svn: 224868
* [Hexagon] Adding post-increment unsigned byte loads.Colin LeMahieu2014-12-263-6/+5
| | | | llvm-svn: 224867
* [Hexagon] Adding post-increment signed byte loads with tests.Colin LeMahieu2014-12-263-12/+110
| | | | llvm-svn: 224866
* [Hexagon] Removing old classes.Colin LeMahieu2014-12-241-80/+0
| | | | llvm-svn: 224795
* [Hexagon] Adding doubleword load.Colin LeMahieu2014-12-234-29/+17
| | | | llvm-svn: 224787
* [Hexagon] Reapplying 224775 load words.Colin LeMahieu2014-12-237-46/+39
| | | | llvm-svn: 224786
* Reverting 224775 until mayLoad flag is addressed.Colin LeMahieu2014-12-236-38/+46
| | | | llvm-svn: 224783
* [Hexagon] Adding word loads.Colin LeMahieu2014-12-236-46/+38
| | | | llvm-svn: 224775
* [Hexagon] Adding signed halfword loads.Colin LeMahieu2014-12-235-30/+20
| | | | llvm-svn: 224774
* [Hexagon] Adding unsigned halfword load.Colin LeMahieu2014-12-235-20/+18
| | | | llvm-svn: 224772
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