summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Hexagon
Commit message (Collapse)AuthorAgeFilesLines
...
* [Hexagon] Maintain kill flags through splitting in expand-condsetsKrzysztof Parzyszek2016-10-281-40/+96
| | | | | | | Do not use LiveIntervals to recalculate kills, because that cannot be done accurately without implicit uses on predicated instructions. llvm-svn: 285409
* [Hexagon] Do not expand ISD::SELECT for HVX vectorsKrzysztof Parzyszek2016-10-272-16/+19
| | | | llvm-svn: 285297
* MachineInstrBundle: Pass iterators to getBundle(Start|End); NFCMatthias Braun2016-10-251-1/+1
| | | | | | | | This is a function to go backwards in a block to find the first instruction in a bundle, so iterator is a more natural choice for parameter/return rather than a reference to a MachineInstruction. llvm-svn: 285051
* Use MachineInstr::mop_iterator instead of MIOperands; NFCMatthias Braun2016-10-245-30/+30
| | | | | | | | (Const)?MIOperands is equivalent to the C++ style MachineInstr::mop_iterator. Use the latter for consistency except for a few callers of MIOperands::analyzePhysReg(). llvm-svn: 285029
* Target: Change various section classifiers in TargetLoweringObjectFile to ↵Peter Collingbourne2016-10-243-45/+47
| | | | | | | | | | | | | | | | take a GlobalObject. These functions are about classifying a global which will actually be emitted, so it does not make sense for them to take a GlobalValue which may for example be an alias. Change the Mach-O object writer and the Hexagon, Lanai and MIPS backends to look through aliases before using TargetLoweringObjectFile interfaces. These are functional changes but all appear to be bug fixes. Differential Revision: https://reviews.llvm.org/D25917 llvm-svn: 285006
* Revert r284972 and remove other defaulted copy/move constructors/=Krzysztof Parzyszek2016-10-241-8/+0
| | | | | | | David Blaikie pointed out that we get them for free without having to write anything. llvm-svn: 284996
* [RDF] Add default move constructors/assignment operatorsKrzysztof Parzyszek2016-10-241-2/+6
| | | | llvm-svn: 284972
* [RDF] Use RegisterId typedef more consistently, NFCKrzysztof Parzyszek2016-10-213-11/+12
| | | | llvm-svn: 284857
* [Hexagon] Handle spills of partially defined double vector registersKrzysztof Parzyszek2016-10-211-21/+36
| | | | | | | | | | | | After register allocation it is possible to have a spill of a register that is only partially defined. That in itself it fine, but creates a problem for double vector registers. Stores of such registers are pseudo instructions that are expanded into pairs of individual vector stores, and in case of a partially defined source, one of the stores may use an entirely undefined register. To avoid this, track the defined parts and only generate actual stores for those. llvm-svn: 284841
* Do a sweep over move ctors and remove those that are identical to the default.Benjamin Kramer2016-10-201-7/+0
| | | | | | | | | | All of these existed because MSVC 2013 was unable to synthesize default move ctors. We recently dropped support for it so all that error-prone boilerplate can go. No functionality change intended. llvm-svn: 284721
* Use __func__ directly now that all supported compilers support itReid Kleckner2016-10-206-11/+11
| | | | | | Remove the portability macro now that it is unused. llvm-svn: 284681
* [RDF] Switch RefMap in liveness calculation to use lane masksKrzysztof Parzyszek2016-10-195-84/+218
| | | | | | | | | | This required reengineering of some of the part of liveness calculation, including fixing some issues caused by the limitations of the previous approach. The current code is not necessarily the fastest, but it should be functionally correct (at least more so than before). The compile-time performance will be addressed in the future. llvm-svn: 284609
* [Hexagon] Handle block live-ins with lane masks in HexagonBlockRangesKrzysztof Parzyszek2016-10-182-11/+28
| | | | llvm-svn: 284522
* The real fix for post-r284255 failuresKrzysztof Parzyszek2016-10-142-3/+2
| | | | llvm-svn: 284264
* Workaround to eliminate check-llvm failures after r284255Krzysztof Parzyszek2016-10-141-0/+1
| | | | llvm-svn: 284262
* [RDF] Switch RegisterRef to be a pair (Register, LaneMask)Krzysztof Parzyszek2016-10-148-255/+236
| | | | | | | | | Use PackedRegisterRef to store the register information in the graph nodes. This commit also removes support for virtual registers. It has never been tested or used. It will be possible to add it back if there is a need. llvm-svn: 284255
* Revert r283690, "MC: Remove unused entities."Peter Collingbourne2016-10-101-1/+1
| | | | llvm-svn: 283814
* Move the global variables representing each Target behind accessor functionMehdi Amini2016-10-097-17/+21
| | | | | | | | This avoids "static initialization order fiasco" Differential Revision: https://reviews.llvm.org/D25412 llvm-svn: 283702
* MC: Remove unused entities.Peter Collingbourne2016-10-091-1/+1
| | | | llvm-svn: 283691
* [Hexagon] Adding change of flow max 1 (cofMax1) TS flag for marking this ↵Colin LeMahieu2016-10-085-4/+16
| | | | | | restriction rather than implying it from TypeJR. llvm-svn: 283665
* [Hexagon][NFC] Using documented instruction type name V4LDST instead of MEMOP.Colin LeMahieu2016-10-073-4/+4
| | | | llvm-svn: 283582
* Target: Remove unused patterns and transforms. NFC.Peter Collingbourne2016-10-071-108/+0
| | | | llvm-svn: 283515
* [Hexagon] NFC Removing 'V4_' prefix from duplex instruction names.Colin LeMahieu2016-10-074-471/+471
| | | | llvm-svn: 283514
* [Hexagon] NFC. Canonicalizing absolute address instruction names.Colin LeMahieu2016-10-064-125/+125
| | | | llvm-svn: 283507
* [Hexagon] Avoid replacing full regs with subregisters in tied operandsKrzysztof Parzyszek2016-10-061-0/+20
| | | | | | Doing so will result in the two-address pass generating incorrect code. llvm-svn: 283463
* [RDF] Replace some expensive copies with references in range-based loopsKrzysztof Parzyszek2016-10-061-7/+7
| | | | llvm-svn: 283446
* [RDF] Replace potentially unclear autos with real typesKrzysztof Parzyszek2016-10-062-59/+53
| | | | llvm-svn: 283445
* [RDF] Fix live def propagation through basic blockKrzysztof Parzyszek2016-10-051-45/+60
| | | | llvm-svn: 283371
* [RDF] Fix liveness propagation through shadowsKrzysztof Parzyszek2016-10-031-29/+7
| | | | | | | | Each shadow only represents data flow that is restricted to its reaching def. Propagating more than that could lead to spurious register liveness, resulting in extra (incorrectly) block live-ins. llvm-svn: 283143
* [RDF] Further improve readability of the graphKrzysztof Parzyszek2016-10-031-11/+14
| | | | | | Print target basic block for a branch. llvm-svn: 283126
* [RDF] Replace RegisterAliasInfo with target-independent code using lane masksKrzysztof Parzyszek2016-10-0310-430/+369
| | | | llvm-svn: 283122
* Use StringRef instead of raw pointers in MCAsmInfo/MCInstrInfo APIs (NFC)Mehdi Amini2016-10-013-4/+4
| | | | llvm-svn: 283018
* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-0126-40/+26
| | | | llvm-svn: 283004
* [RDF] Add "dead" flag to node attributesKrzysztof Parzyszek2016-09-273-14/+48
| | | | llvm-svn: 282520
* [RDF] Special treatment of exception handling registersKrzysztof Parzyszek2016-09-272-3/+65
| | | | | | | | | | | | A landing pad can have live-in registers that are defined by the runtime, not the program (exception pointer register and exception selector register). Make sure to recognize that case and not link these registers with any defs in the program. Each landing pad will have phi nodes added at the beginning to provide definitions of these registers, but the uses of those phi nodes will not have any reaching defs. llvm-svn: 282519
* [RDF] Add initial support for lane masks in the DFGKrzysztof Parzyszek2016-09-225-62/+163
| | | | | | | Use lane masks for calculating covering and aliasing of register references. llvm-svn: 282194
* [Hexagon] Remove USR_OVF from CtrRegs register classKrzysztof Parzyszek2016-09-221-1/+4
| | | | | | | | | USR_OVF is a subregister of USR, which is a member of CtrRegs. Having both a register and its proper subregister in the same register class has bad consequences for lane mask calculation: based solely on the lane mask info, USR_OVF would not appear to be a subregister of USR. llvm-svn: 282192
* [RDF] Print the function name for calls in dumpsKrzysztof Parzyszek2016-09-221-3/+18
| | | | llvm-svn: 282191
* [RDF] Use uint32_t for register numbers instead of unsignedKrzysztof Parzyszek2016-09-222-8/+8
| | | | llvm-svn: 282190
* [Hexagon] segv while processing SUnit with nullNodePtrRon Lieberman2016-09-171-0/+4
| | | | | | Added BoundaryNode check to isBestZeroLatency function. llvm-svn: 281825
* Defer asm errors to post-statement failureNirav Dave2016-09-161-25/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recommitting after fixing AsmParser initialization and X86 inline asm error cleanup. Allow errors to be deferred and emitted as part of clean up to simplify and shorten Assembly parser code. This will allow error messages to be emitted in helper functions and be modified by the caller which has better context. As part of this many minor cleanups to the Parser: * Unify parser cleanup on error * Add Workaround for incorrect return values in ParseDirective instances * Tighten checks on error-signifying return values for parser functions and fix in-tree TargetParsers to be more consistent with the changes. * Fix AArch64 test cases checking for spurious error messages that are now fixed. These changes should be backwards compatible with current Target Parsers so long as the error status are correctly returned in appropriate functions. Reviewers: rnk, majnemer Subscribers: aemerson, jyknight, llvm-commits Differential Revision: https://reviews.llvm.org/D24047 llvm-svn: 281762
* Move the Mangler from the AsmPrinter down to TLOF and clean up theEric Christopher2016-09-162-20/+12
| | | | | | TLOF API accordingly. llvm-svn: 281708
* Finish renaming remaining analyzeBranch functionsMatt Arsenault2016-09-143-9/+9
| | | | llvm-svn: 281535
* Make analyzeBranch family of instruction names consistentMatt Arsenault2016-09-143-9/+9
| | | | | | | analyzeBranch was renamed to use lowercase first, rename the related set to match. llvm-svn: 281506
* AArch64: Use TTI branch functions in branch relaxationMatt Arsenault2016-09-142-4/+11
| | | | | | | | | The main change is to return the code size from InsertBranch/RemoveBranch. Patch mostly by Tim Northover llvm-svn: 281505
* getVectorElementType().getSizeInBits() -> getScalarSizeInBits() ; NFCISanjay Patel2016-09-142-2/+2
| | | | llvm-svn: 281495
* getValueType().getSizeInBits() -> getValueSizeInBits() ; NFCISanjay Patel2016-09-141-4/+3
| | | | llvm-svn: 281493
* This reapplies r281304. The issue was that I had missedSjoerd Meijer2016-09-142-7/+4
| | | | | | to copy the new isAdd field in the tablegen data structure. llvm-svn: 281447
* [Hexagon] Better handling of HVX vector loweringKrzysztof Parzyszek2016-09-132-4/+17
| | | | | | | - Expand SELECT_CC and BR_CC for vector types. - Implement TLI::isShuffleMaskLegal. llvm-svn: 281397
* Revert r281336 (and r281337), it caused PR30372.Nico Weber2016-09-131-29/+25
| | | | llvm-svn: 281361
OpenPOWER on IntegriCloud