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* [Hexagon] Add patterns for shifts of v2i16Krzysztof Parzyszek2018-12-141-0/+12
| | | | | | This fixes https://llvm.org/PR39983. llvm-svn: 349202
* [Hexagon] Use IMPLICIT_DEF to any-extend 32-bit values to 64 bitsKrzysztof Parzyszek2018-12-141-23/+25
| | | | llvm-svn: 349199
* [Hexagon] Couple of fixes in optimize addressing modeKrzysztof Parzyszek2018-12-101-16/+21
| | | | | | | | | | - Check if an operand is an immediate before calling getImm. Some operands that take constant values can actually have global symbols or other constant expressions. - When a load-constant instruction can be folded into users, make sure to only delete it when all users have been successfully converted. llvm-svn: 348802
* Revert "[Hexagon] Check if operand is an immediate before getImm"Krzysztof Parzyszek2018-12-101-15/+12
| | | | | | This reverts r348787. The patch wasn't quite correct. llvm-svn: 348792
* [Hexagon] Check if operand is an immediate before getImmKrzysztof Parzyszek2018-12-101-12/+15
| | | | llvm-svn: 348787
* [Hexagon] Add patterns for any_extend from i1 and short vectors of i1Krzysztof Parzyszek2018-12-101-29/+28
| | | | llvm-svn: 348785
* [Hexagon] Fix post-ra expansion of PS_wselectKrzysztof Parzyszek2018-12-071-1/+0
| | | | llvm-svn: 348655
* [Targets] Add errors for tiny and kernel codemodel on targets that don't ↵David Green2018-12-071-7/+2
| | | | | | | | | | | support them Adds fatal errors for any target that does not support the Tiny or Kernel codemodels by rejigging the getEffectiveCodeModel calls. Differential Revision: https://reviews.llvm.org/D50141 llvm-svn: 348585
* Fix gcc7.3 -Wparentheses warning. NFCI.Simon Pilgrim2018-12-071-3/+3
| | | | llvm-svn: 348581
* [Hexagon] Add intrinsics for Hexagon V66Krzysztof Parzyszek2018-12-051-0/+30
| | | | llvm-svn: 348413
* [Hexagon] Add instruction definitions for Hexagon V66Krzysztof Parzyszek2018-12-0516-500/+2763
| | | | llvm-svn: 348411
* [Hexagon] Foundation of support for Hexagon V66Krzysztof Parzyszek2018-12-0514-125/+226
| | | | llvm-svn: 348407
* [Hexagon] Remove unused checker functions from asm parserKrzysztof Parzyszek2018-12-041-2/+0
| | | | llvm-svn: 348269
* Fix MSVC "unknown pragma" warning. NFCI.Simon Pilgrim2018-12-041-0/+6
| | | | llvm-svn: 348256
* [Hexagon] Switch to auto-generated intrinsic definitions and patternsKrzysztof Parzyszek2018-12-033-1233/+3613
| | | | llvm-svn: 348206
* [Hexagon] Extract operand decoders into a separate file, NFCKrzysztof Parzyszek2018-12-032-56/+74
| | | | | | | These decoders are automatically generated. Keeping them separated makes updating architectures easier. llvm-svn: 348196
* [Hexagon] Remove unused encodings, NFCKrzysztof Parzyszek2018-12-031-741/+114
| | | | llvm-svn: 348193
* [Hexagon] Update timing classesKrzysztof Parzyszek2018-12-035-5770/+5651
| | | | llvm-svn: 348183
* [Hexagon] Change instruction type field in TSFlags to 7 bitsKrzysztof Parzyszek2018-12-035-182/+177
| | | | llvm-svn: 348171
* [Hexagon] Add HasV5 predicate for compatibility with auto-generated filesKrzysztof Parzyszek2018-12-031-6/+6
| | | | llvm-svn: 348167
* [Hexagon] Remove unused operand definitions, NFCKrzysztof Parzyszek2018-12-031-8/+1
| | | | llvm-svn: 348163
* [Hexagon] Some formatting changes, NFCKrzysztof Parzyszek2018-12-032-5/+3
| | | | llvm-svn: 348162
* [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operandFrancis Visoiu Mistrih2018-11-283-27/+30
| | | | | | | | | | | | | | | | | | Currently, instructions doing memory accesses through a base operand that is not a register can not be analyzed using `TII::getMemOpBaseRegImmOfs`. This means that functions such as `TII::shouldClusterMemOps` will bail out on instructions using an FI as a base instead of a register. The goal of this patch is to refactor all this to return a base operand instead of a base register. Then in a separate patch, I will add FI support to the mem op clustering in the MachineScheduler. Differential Revision: https://reviews.llvm.org/D54846 llvm-svn: 347746
* [x86] allow vector load narrowing with multi-use valuesSanjay Patel2018-11-101-0/+4
| | | | | | | | | | | | | | | | | | | | | | This is a long-awaited follow-up suggested in D33578. Since then, we've picked up even more opportunities for vector narrowing from changes like D53784, so there are a lot of test diffs. Apart from 2-3 strange cases, these are all wins. I've structured this to be no-functional-change-intended for any target except for x86 because I couldn't tell if AArch64, ARM, and AMDGPU would improve or not. All of those targets have existing regression tests (4, 4, 10 files respectively) that would be affected. Also, Hexagon overrides the shouldReduceLoadWidth() hook, but doesn't show any regression test diffs. The trade-off is deciding if an extra vector load is better than a single wide load + extract_subvector. For x86, this is almost always better (on paper at least) because we often can fold loads into subsequent ops and not increase the official instruction count. There's also some unknown -- but potentially large -- benefit from using narrower vector ops if wide ops are implemented with multiple uops and/or frequency throttling is avoided. Differential Revision: https://reviews.llvm.org/D54073 llvm-svn: 346595
* [Hexagon] Fix some -Wunused-function with LLVM_DUMP_METHOD and -Wunused-variableFangrui Song2018-11-092-4/+9
| | | | llvm-svn: 346543
* [Hexagon] Fix unused variable warning in release buildsJordan Rupprecht2018-11-091-0/+1
| | | | llvm-svn: 346537
* [Hexagon] Implement noreturn optimizationBrendon Cahoon2018-11-094-1/+39
| | | | | | | | | | | Eliminate the stack frame in functions with the noreturn nounwind attributes, and when the noreturn-stack-elim target feature is enabled. This reduces the code and stack space needed for noreturn functions. Differential Revision: https://reviews.llvm.org/D54210 llvm-svn: 346532
* [Hexagon] Place globals with explicit .sdata section in small dataKrzysztof Parzyszek2018-11-091-5/+10
| | | | | | | | Both -fPIC and -G0 disable placement of globals in small data section, but if a global has an explicit section assigmnent placing it in small data, it should go there anyway. llvm-svn: 346523
* LivePhysRegs/IfConversion: Change some types from unsigned to MCPhysReg; NFCMatthias Braun2018-11-061-1/+1
| | | | | | | | Change the type in a couple of lists and sets that only store physical registers from unsigned to MCPhysRegs. The later is only 16bits and saves us a bit of memory. llvm-svn: 346254
* [TargetLowering] Change TargetLoweringBase::getPreferredVectorAction to take ↵Craig Topper2018-11-053-4/+4
| | | | | | | | an MVT instead of an EVT. NFC The main caller of this already has an MVT and several targets called getSimpleVT inside without checking isSimple. This makes the simpleness explicit. llvm-svn: 346180
* [SelectionDAG] Remove special methods for creating *_EXTEND_VECTOR_INREG ↵Craig Topper2018-11-041-1/+2
| | | | | | | | | | nodes. Move asserts into getNode. These methods were just wrappers around getNode with additional asserts (identical and repeated 3 times). But getNode already has a switch that can be used to hold these asserts that allows them to be shared for all 3 opcodes. This also enables checking on the places that create these nodes without using the wrappers. The rest of the patch is just changing all callers to use getNode directly. llvm-svn: 346087
* [Hexagon] Do not reduce load size for globals in small-dataKrzysztof Parzyszek2018-11-022-0/+18
| | | | | | | | | | | | Small-data (i.e. GP-relative) loads and stores allow 16-bit scaled offset. For a load of a value of type T, the small-data area is equivalent to an array "T sdata[65536]". This implies that objects of smaller sizes need to be closer to the beginning of sdata, while larger objects may be farther away, or otherwise the offset may be insufficient to reach it. Similarly, an object of a larger size should not be accessed via a load of a smaller size. llvm-svn: 345975
* [Hexagon] Remove unintended fallthrough from MC duplex codeReid Kleckner2018-11-011-5/+5
| | | | | | | | | | | | I added these annotations in r345878 because I wasn't sure if the fallthrough was intended. Krzysztof Parzyszek confirmed that they should be breaks, so that's what this patch does. Reviewers: kparzysz Differential Revision: https://reviews.llvm.org/D53991 llvm-svn: 345883
* Fix clang -Wimplicit-fallthrough warnings across llvm, NFCReid Kleckner2018-11-015-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch should not introduce any behavior changes. It consists of mostly one of two changes: 1. Replacing fall through comments with the LLVM_FALLTHROUGH macro 2. Inserting 'break' before falling through into a case block consisting of only 'break'. We were already using this warning with GCC, but its warning behaves slightly differently. In this patch, the following differences are relevant: 1. GCC recognizes comments that say "fall through" as annotations, clang doesn't 2. GCC doesn't warn on "case N: foo(); default: break;", clang does 3. GCC doesn't warn when the case contains a switch, but falls through the outer case. I will enable the warning separately in a follow-up patch so that it can be cleanly reverted if necessary. Reviewers: alexfh, rsmith, lattner, rtrieu, EricWF, bollu Differential Revision: https://reviews.llvm.org/D53950 llvm-svn: 345882
* Annotate possibly unintended fallthroughs in Hexagon MC code, NFCReid Kleckner2018-11-011-0/+6
| | | | | | | | | | | | | | | | Clang's -Wimplicit-fallthrough check fires on these switch cases. GCC does not warn when a case body that ends in a switch falls through to a case label of an outer switch. It's not clear if these fall throughs are truly intended. The Hexagon tests pass regardless of whether these case blocks fall through or break. For now, I have applied the intended fallthrough annotation macro with a FIXME comment to unblock enabling the warning. I will send a follow-up patch that converts them to breaks to the Hexagon maintainers. llvm-svn: 345878
* [Hexagon] Fix MO_JumpTable const extender conversionReid Kleckner2018-11-011-0/+1
| | | | | | | | | | Previously this case fell through to unreachable, so it is clearly not covered by any test case in LLVM. It may be dynamically unreachable, in fact. However, if it were to run, this is what it would logically do. The assert suggests that the intended behavior was not to allow folding offsets from jump table indices, which makes sense. llvm-svn: 345868
* [Hexagon] Make sure not to use GP-relative addressing with PICKrzysztof Parzyszek2018-10-313-4/+10
| | | | | | | Make sure that -relocation-model=pic prevents use of GP-relative addressing modes. llvm-svn: 345731
* [LV] Support vectorization of interleave-groups that require an epilog underDorit Nuzman2018-10-312-4/+7
| | | | | | | | | | | | | | | | | | | | | | optsize using masked wide loads Under Opt for Size, the vectorizer does not vectorize interleave-groups that have gaps at the end of the group (such as a loop that reads only the even elements: a[2*i]) because that implies that we'll require a scalar epilogue (which is not allowed under Opt for Size). This patch extends the support for masked-interleave-groups (introduced by D53011 for conditional accesses) to also cover the case of gaps in a group of loads; Targets that enable the masked-interleave-group feature don't have to invalidate interleave-groups of loads with gaps; they could now use masked wide-loads and shuffles (if that's what the cost model selects). Reviewers: Ayal, hsaito, dcaballe, fhahn Reviewed By: Ayal Differential Revision: https://reviews.llvm.org/D53668 llvm-svn: 345705
* Revert r345169 [along with its llvm counterpart r345170] as it makes Halide ↵Alina Sbirlea2018-10-271-1/+1
| | | | | | builds timeout. llvm-svn: 345447
* [Hexagon] Add missing assignment to Itinerary in Call_nrBrendon Cahoon2018-10-271-0/+1
| | | | | | | | | | | | The class definition for Call_nr has the itinerary as a parameter, but the value is never assigned to the Itinerary field for the instruction. This means the compiler is unable to schedule and packetize the instruction correctly because these instrution will not have any resource descritions. I don't have a specific test case, but the ps_call_nr.ll test failed with a proposed patch. llvm-svn: 345442
* [Hexagon] Flip hexagon-autohvx to be true by defaultKrzysztof Parzyszek2018-10-241-1/+1
| | | | | | | | | | | This will allow other generators of LLVM IR to use the auto-vectorizer without having to change that flag. Note: on its own, this patch will enable auto-vectorization on Hexagon in all cases, regardless of the -fvectorize flag. There is a companion clang patch that together with this one forms an NFC for clang users. llvm-svn: 345169
* [Hexagon] Remove support for V4Krzysztof Parzyszek2018-10-1923-757/+567
| | | | llvm-svn: 344791
* Use llvm::{all,any,none}_of instead std::{all,any,none}_of. NFCFangrui Song2018-10-191-1/+1
| | | | llvm-svn: 344774
* recommit 344472 after fixing build failure on ARM and PPC.Dorit Nuzman2018-10-142-4/+4
| | | | llvm-svn: 344475
* revert 344472 due to failures.Dorit Nuzman2018-10-142-4/+4
| | | | llvm-svn: 344473
* [IAI,LV] Add support for vectorizing predicated strided accesses using maskedDorit Nuzman2018-10-142-4/+4
| | | | | | | | | | | | | | | | | | | | | | | interleave-group The vectorizer currently does not attempt to create interleave-groups that contain predicated loads/stores; predicated strided accesses can currently be vectorized only using masked gather/scatter or scalarization. This patch makes predicated loads/stores candidates for forming interleave-groups during the Loop-Vectorizer's analysis, and adds the proper support for masked-interleave- groups to the Loop-Vectorizer's planning and transformation stages. The patch also extends the TTI API to allow querying the cost of masked interleave groups (which each target can control); Targets that support masked vector loads/ stores may choose to enable this feature and allow vectorizing predicated strided loads/stores using masked wide loads/stores and shuffles. Reviewers: Ayal, hsaito, dcaballe, fhahn, javed.absar Reviewed By: Ayal Differential Revision: https://reviews.llvm.org/D53011 llvm-svn: 344472
* [Hexagon] Restrict compound instructions with constant value.Sumanth Gundapaneni2018-10-111-10/+27
| | | | | | | | | | Having a constant value operand in the compound instruction is not always profitable. This patch improves coremark by ~4% on Hexagon. Differential Revision: https://reviews.llvm.org/D53152 llvm-svn: 344284
* [Hexagon] Eliminate potential sources of non-determinism in HCEKrzysztof Parzyszek2018-10-111-9/+33
| | | | | | | | | Also, avoid comparing GUIDs when ordering global addresses, because source file location can cause different GUID to be calculated. As a result, a pair of symbols can compare "less" in one directory, but "greater" in another. llvm-svn: 344271
* Replace most users of UnknownSize with LocationSize::unknown(); NFCGeorge Burgess IV2018-10-101-1/+1
| | | | | | | | | | | | Moving away from UnknownSize is part of the effort to migrate us to LocationSizes (e.g. the cleanup promised in D44748). This doesn't entirely remove all of the uses of UnknownSize; some uses require tweaks to assume that UnknownSize isn't just some kind of int. This patch is intended to just be a trivial replacement for all places where LocationSize::unknown() will Just Work. llvm-svn: 344186
* [TargetRegisterInfo] Remove temporary hook enableMultipleCopyHints()Jonas Paulsson2018-10-051-2/+0
| | | | | | | | | | | | Finally all targets are enabling multiple regalloc hints, so the hook to disable this can now be removed. NFC. Review: Simon Pilgrim https://reviews.llvm.org/D52316 llvm-svn: 343851
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