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* Move RDF from Hexagon to CodegenScott Constable2020-06-241-3/+3
| | | | | | | | RDF is designed to be target agnostic. Therefore it would be useful to have it available for other targets, such as X86. Based on a previous patch by Krzysztof Parzyszek Differential Revision: https://reviews.llvm.org/D75932
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to ↵Daniel Sanders2019-08-011-2/+2
| | | | | | llvm::Register as started by r367614. NFC llvm-svn: 367633
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931
* [RDF] Clear the renamable flag when copy propagating reserved registersKrzysztof Parzyszek2018-01-301-2/+6
| | | | llvm-svn: 323831
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-2/+2
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-08-011-9/+14
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 309746
* [RDF] Use faster version of findBlockKrzysztof Parzyszek2017-04-191-1/+1
| | | | llvm-svn: 300704
* [RDF] Remove the map of reaching defs from copy propagationKrzysztof Parzyszek2017-03-101-52/+20
| | | | | | Use Liveness::getNearestAliasedRef to find the reaching def instead. llvm-svn: 297526
* [RDF] Differentiate between defining and clobbering nodesKrzysztof Parzyszek2017-02-161-1/+1
| | | | | | | | | | Defining nodes should not alias with one another, while clobbering nodes can. When pushing defs on stacks, push clobbers first, link non-clobbering defs, then push the defs. The data flow in a statement is now: uses -> clobbers -> defs. llvm-svn: 295356
* [RDF] Switch RegisterRef to be a pair (Register, LaneMask)Krzysztof Parzyszek2016-10-141-38/+27
| | | | | | | | | Use PackedRegisterRef to store the register information in the graph nodes. This commit also removes support for virtual registers. It has never been tested or used. It will be possible to add it back if there is a need. llvm-svn: 284255
* [RDF] Replace RegisterAliasInfo with target-independent code using lane masksKrzysztof Parzyszek2016-10-031-2/+2
| | | | llvm-svn: 283122
* [hexagon] Move BlockRanges and RDF stuff into the llvm namespace.Benjamin Kramer2016-05-271-3/+2
| | | | | | No functional change intended. llvm-svn: 270980
* [RDF] Handle undefined registers in RDF copy propagationKrzysztof Parzyszek2016-04-281-1/+6
| | | | | | | When updating the graph, make sure that new uses without reaching defs are handled correctly. llvm-svn: 267891
* [RDF] Improvements to copy propagationKrzysztof Parzyszek2016-01-181-71/+138
| | | | | | | - Allow any instruction to define equality between registers. - Keep the DFG updated. llvm-svn: 258075
* RDF: Copy propagationKrzysztof Parzyszek2016-01-121-0/+180
This is a very limited implementation of DFG-based copy propagation. It only handles actual COPY instructions (does not handle other equivalents such as add-immediate with a 0 operand). The major limitation is that it does not update the DFG: that will be the change required to make it more robust (hopefully coming up soon). llvm-svn: 257490
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