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path: root/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
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* Include what you use in HexagonMCCodeEmitter.cppDmitri Gribenko2019-06-031-1/+0
| | | | | | | | | HexagonMCCodeEmitter.cpp was not using any APIs from Hexagon.h. Doing so is problematic from include-what-you-use perspective, but it is also a layering issue (it creates a dependency cycle between the primary Hexagon target library and the MCTargetDesc library). llvm-svn: 362386
* Use bitset for assembler predicatesStanislav Mekhanoshin2019-03-111-1/+1
| | | | | | | | | | | | | | AMDGPU target run out of Subtarget feature flags hitting the limit of 64. AssemblerPredicates uses at most uint64_t for their representation. At the same time CodeGen has exhausted this a long time ago and switched to a FeatureBitset with the current limit of 192 bits. This patch completes transition to the bitset for feature bits extending it to asm matcher and MC code emitter. Differential Revision: https://reviews.llvm.org/D59002 llvm-svn: 355839
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* Support: Simplify endian stream interface. NFCI.Peter Collingbourne2018-05-181-1/+1
| | | | | | | | | | | | Provide some free functions to reduce verbosity of endian-writing a single value, and replace the endianness template parameter with a field. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47032 llvm-svn: 332757
* Fix up a misleading format warning.Eric Christopher2018-05-161-1/+1
| | | | llvm-svn: 332521
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-12/+11
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* [Hexagon] Check the end of the correct container (fix typo)Krzysztof Parzyszek2018-05-091-3/+1
| | | | llvm-svn: 331907
* [Hexagon] Fix sanitizer error about using -1u in variable of enum typeKrzysztof Parzyszek2018-05-091-4/+4
| | | | llvm-svn: 331887
* [Hexagon] Simplify MCCodeEmitter, move data to tablesKrzysztof Parzyszek2018-05-091-571/+544
| | | | llvm-svn: 331883
* [Hexagon] Move clamping of extended operands directly to MC code emitterKrzysztof Parzyszek2018-05-071-3/+26
| | | | llvm-svn: 331653
* [Hexagon] Make getMemAccessSize return size in bytesKrzysztof Parzyszek2017-09-141-10/+10
| | | | | | | | It used to return the actual field value from the instruction descriptor. There is no reason for that, that value is not interesting in any way and the specifics of its encoding in the descriptor should not be exposed. llvm-svn: 313257
* [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-08-011-38/+43
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 309746
* [Hexagon] Mark raise_relocation_error as NORETURN.Florian Hahn2017-07-261-0/+1
| | | | | | | | | | | | | | | | Summary: This silences a couple of implicit fallthrough warnings with GCC 7.1 in this file. Reviewers: colinl, kparzysz Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35889 llvm-svn: 309129
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
* [Hexagon] Remove C6 and C7 as separate registersKrzysztof Parzyszek2017-05-051-8/+0
| | | | | | | These are M0 and M1. Removing duplicated registers reduces the number of explicit register aliasing. llvm-svn: 302306
* [Hexagon] Change iconst to emit 27bit relocationKrzysztof Parzyszek2017-05-021-2/+2
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301956
* [Hexagon] Add extenders for GD_PLT_B22_PCREL and LD_PLT_B22_PCRELKrzysztof Parzyszek2017-05-021-2/+17
| | | | | | Patch by Sid Manning. llvm-svn: 301955
* Fix 'variable set but not used' warning when assertions are disabled.Simon Pilgrim2017-02-191-0/+2
| | | | llvm-svn: 295585
* [Hexagon] Update MCTargetDescKrzysztof Parzyszek2017-02-061-60/+15
| | | | | | | | | | Changes include: - Updates to the instruction descriptor flags. - Improvements to the packet shuffler and checker. - Updates to the handling of certain relocations. - Better handling of duplex instructions. llvm-svn: 294226
* [Hexagon] Adding opExtentBits and opExtentAlign to GPrel instructionsKrzysztof Parzyszek2017-02-021-1/+25
| | | | | | Patch by Colin LeMahieu. llvm-svn: 293933
* [Hexagon] Fix relocation kind for extended predicated callsKrzysztof Parzyszek2017-02-021-5/+7
| | | | | | Patch by Sid Manning. llvm-svn: 293931
* [Hexagon] Remove A4_ext_* pseudo instructionsKrzysztof Parzyszek2017-02-021-15/+20
| | | | | | Patch by Colin LeMahieu. llvm-svn: 293929
* [Hexagon] Emitting individual instructions without copying themKrzysztof Parzyszek2017-02-021-94/+79
| | | | | | Patch by Colin LeMahieu. llvm-svn: 293899
* [Hexagon] Rename TypeCOMPOUND to TypeCJKrzysztof Parzyszek2017-02-021-1/+1
| | | | llvm-svn: 293894
* Check that emitted instructions meet their predicates on all targets except ↵Daniel Sanders2016-11-191-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | ARM, Mips, and X86. Summary: * ARM is omitted from this patch because this check appears to expose bugs in this target. * Mips is omitted from this patch because this check either detects bugs or deliberate emission of instructions that don't satisfy their predicates. One deliberate use is the SYNC instruction where the version with an operand is correctly defined as requiring MIPS32 while the version without an operand is defined as an alias of 'SYNC 0' and requires MIPS2. * X86 is omitted from this patch because it doesn't use the tablegen-erated MCCodeEmitter infrastructure. Patches for ARM and Mips will follow. Depends on D25617 Reviewers: tstellarAMD, jmolloy Subscribers: wdng, jmolloy, aemerson, rengolin, arsenm, jyknight, nemanjai, nhaehnle, tstellarAMD, llvm-commits Differential Revision: https://reviews.llvm.org/D25618 llvm-svn: 287439
* [Hexagon] Handle double-vector registers as new-value producersKrzysztof Parzyszek2016-04-281-3/+27
| | | | | | Patch by Colin LeMahieu. llvm-svn: 267897
* [Hexagon] Properly encode registers in duplex instructionsKrzysztof Parzyszek2016-03-211-6/+15
| | | | llvm-svn: 263980
* [Hexagon] Remove redundant check.Chad Rosier2016-02-181-2/+2
| | | | llvm-svn: 261232
* [Hexagon] Adding relocation for code size, cold path optimization allowing a ↵Colin LeMahieu2016-02-161-0/+7
| | | | | | | | | | | | 23-bit 4-byte aligned relocation to be a valid instruction encoding. The usual way to get a 32-bit relocation is to use a constant extender which doubles the size of the instruction, 4 bytes to 8 bytes. Another way is to put a .word32 and mix code and data within a function. The disadvantage is it's not a valid instruction encoding and jumping over it causes prefetch stalls inside the hardware. This relocation packs a 23-bit value in to an "r0 = add(rX, #a)" instruction by overwriting the source register bits. Since r0 is the return value register, if this instruction is placed after a function call which return void, r0 will be filled with an undefined value, the prefetch won't be confused, and the callee can access the constant value by way of the link register. llvm-svn: 261006
* [Hexagon] Wrapping all MCExprs inside MCOperands within HexagonMCExpr to ↵Colin LeMahieu2016-02-151-3/+2
| | | | | | simplify handling and allow flags on the expression. llvm-svn: 260902
* [MC] Merge VK_PPC_TPREL in to generic VK_TPREL.Colin LeMahieu2016-02-101-17/+17
| | | | | | Differential Revision: http://reviews.llvm.org/D17038 llvm-svn: 260401
* [Hexagon] Fixing relocation generation and adding tests.Colin LeMahieu2016-02-091-176/+216
| | | | llvm-svn: 260259
* [Hexagon] Add check for nullptr in getFixupNoBitsKrzysztof Parzyszek2016-01-111-15/+15
| | | | llvm-svn: 257338
* Replace uint16_t with the MCPhysReg typedef in many places. A lot of ↵Craig Topper2015-12-051-1/+1
| | | | | | physical register arrays already use this typedef. llvm-svn: 254843
* [Hexagon] Remove redundant local variable.Tilmann Scheller2015-11-201-4/+2
| | | | | | Identified by the Clang static analyzer. llvm-svn: 253660
* [Hexagon] Fixing compound register printing and reenabling more tests.Colin LeMahieu2015-11-101-0/+16
| | | | llvm-svn: 252574
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-1/+1
| | | | | | Apparently, the style needs to be agreed upon first. llvm-svn: 240390
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-1/+1
| | | | | | | | | | | | | The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! llvm-svn: 240137
* [Hexagon] PC-relative offsets are relative to packet start rather than the ↵Colin LeMahieu2015-06-151-3/+38
| | | | | | offset of the relocation. Set relocation addend and check it's correct in the ELF. llvm-svn: 239769
* [Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.Colin LeMahieu2015-06-051-0/+82
| | | | llvm-svn: 239161
* Revert r239095 incorrect test tree.Colin LeMahieu2015-06-041-82/+0
| | | | llvm-svn: 239102
* [Hexagon] Adding functionality for duplexing. Duplexing is a way to ↵Colin LeMahieu2015-06-041-0/+82
| | | | | | compress commonly used pairs of instructions in order to reduce code size. The test case duplex.ll normally would be 8 bytes, assign register to 0 and jump to link register. After duplexing this is only 4 bytes. This also tests the HexagonMCShuffler code path which is used to make sure duplexed instructions still follow slot requirements. llvm-svn: 239095
* Replace custom fixed endian to raw_ostream emission with EndianStream.Benjamin Kramer2015-06-041-10/+2
| | | | | | Less code, clearer and more efficient. No functionality change intended. llvm-svn: 239040
* MC: Clean up MCExpr naming. NFC.Jim Grosbach2015-05-301-1/+1
| | | | llvm-svn: 238634
* [Hexagon] Disassembling, printing, and emitting instructions a whole-bundle ↵Colin LeMahieu2015-05-291-15/+110
| | | | | | at a time which is the semantic unit for Hexagon. Fixing tests to use the new format. Disabling tests in the direct object emission path for a followup patch. llvm-svn: 238556
* MC: Update MCCodeEmitter naming. NFC.Jim Grosbach2015-05-151-1/+1
| | | | | | s/EncodeInstruction/encodeInstruction/ llvm-svn: 237469
* MC: Update MCFixup naming. NFC.Jim Grosbach2015-05-151-1/+1
| | | | | | s/MCFixup::Create/MCFixup::create/ llvm-svn: 237468
* [Hexagon] Removing variable unused in release.Colin LeMahieu2015-05-011-2/+1
| | | | llvm-svn: 236351
* [Hexagon] Adding expression MC emission and removing XFAIL from test that ↵Colin LeMahieu2015-05-011-4/+445
| | | | | | hits this code path. llvm-svn: 236348
* Remove the use of the subtarget in MCCodeEmitter creation andEric Christopher2015-03-101-8/+2
| | | | | | | update all ports accordingly. Required a couple of small rewrites in handling subtarget features during creation in PPC. llvm-svn: 231861
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