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path: root/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
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* [Hexagon] Add a "generic" cpuBrendon Cahoon2018-06-261-0/+1
* [Hexagon] Remove 'T' from HasVNN predicates, NFCKrzysztof Parzyszek2018-06-201-5/+5
* [Hexagon] Remove unused flag from subtarget and (non)corresponding testKrzysztof Parzyszek2018-05-151-5/+0
* [Hexagon] Add a target feature for memop generationKrzysztof Parzyszek2018-05-141-11/+0
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-2/+2
* [Hexagon] Assertion failure in HexagonSubtarget.cppKrzysztof Parzyszek2018-03-261-7/+7
* [Pipeliner] Use latency to compute RecMIIKrzysztof Parzyszek2018-03-261-12/+16
* [Hexagon] Generalize DAG mutation for function callsKrzysztof Parzyszek2018-03-211-18/+38
* [Hexagon] Improve scheduling based on register pressureKrzysztof Parzyszek2018-03-201-5/+7
* [Hexagon] Add support for Hexagon V65Krzysztof Parzyszek2017-12-111-1/+7
* [Hexagon] Implement HexagonSubtarget::useAA()Krzysztof Parzyszek2017-11-301-1/+9
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-301-4/+4
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-7/+7
* [Hexagon] New HVX target features.Sumanth Gundapaneni2017-10-181-14/+2
* [Hexagon] Update Hexagon ArchEnum and sync some downstream changes(NFC)Sumanth Gundapaneni2017-10-181-6/+6
* [Hexagon] Fix initialization of HexagonSubtargetKrzysztof Parzyszek2017-09-261-36/+18
* [Hexagon] Switch to parameterized register classes for HVXKrzysztof Parzyszek2017-09-151-1/+2
* [Hexagon] Check for potential bank conflicts in post-RA schedulingKrzysztof Parzyszek2017-08-281-0/+51
* [Hexagon] Break up DAG mutations into separate classes, move to subtargetKrzysztof Parzyszek2017-08-281-47/+126
* [Target] Fix some Clang-tidy modernize-use-using and Include What You Use war...Eugene Zelenko2017-06-191-13/+19
* [Hexagon] Disable predicated calls by defaultKrzysztof Parzyszek2017-05-051-0/+8
* [Hexagon] Use automatically-generated scheduling information for HVXKrzysztof Parzyszek2017-05-031-125/+173
* [Hexagon] Introduce Hexagon V62Krzysztof Parzyszek2017-02-101-0/+1
* [Hexagon] Add DAG mutations for machine pipelinerKrzysztof Parzyszek2016-12-221-0/+5
* [Hexagon] segv while processing SUnit with nullNodePtrRon Lieberman2016-09-171-0/+4
* [Hexagon] Enable subregister liveness trackingKrzysztof Parzyszek2016-08-241-1/+1
* [Hexagon] Rename the HEXAGON_MC namespace to Hexagon_MC, NFCKrzysztof Parzyszek2016-08-191-1/+1
* Replace MachineInstr* with MachineInstr& in TargetInstrInfo, NFCKrzysztof Parzyszek2016-08-011-3/+3
* [Hexagon] Referencify MachineInstr in HexagonInstrInfo, NFCKrzysztof Parzyszek2016-07-291-19/+19
* [Hexagon] Add target feature to generate long callsKrzysztof Parzyszek2016-07-251-0/+7
* [Hexagon] Use loop data prefetch on HexagonKrzysztof Parzyszek2016-07-221-0/+8
* [Hexagon] Fix zero latency instructions with multiple predecessorsKrzysztof Parzyszek2016-07-181-37/+60
* [Hexagon] Handle instruction latency for 0 or 2 cyclesKrzysztof Parzyszek2016-07-151-0/+159
* [Hexagon] Add a scheduling DAG mutationKrzysztof Parzyszek2016-07-151-0/+53
* [Hexagon] Add option to enable subregister liveness trackingKrzysztof Parzyszek2016-05-281-0/+9
* [Hexagon] Subtarget features/default CPU correctionsKrzysztof Parzyszek2015-12-141-3/+1
* Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the defaultKrzysztof Parzyszek2015-11-251-31/+54
* [Hexagon] Bring HexagonInstrInfo up to dateKrzysztof Parzyszek2015-11-241-4/+5
* Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and r...Daniel Sanders2015-09-151-1/+1
* Re-commit r247683: Replace Triple with a new TargetTuple in MCTargetDesc/* an...Daniel Sanders2015-09-151-1/+1
* Revert r247684 - Replace Triple with a new TargetTuple ...Daniel Sanders2015-09-151-1/+1
* Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.Daniel Sanders2015-09-151-1/+1
* Remove getDataLayout() from TargetSelectionDAGInfo (had no users)Mehdi Amini2015-07-091-1/+1
* Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and create*MC...Daniel Sanders2015-06-101-2/+2
* Remove more superfluous .str() and replace std::string concatenation with Twine.Yaron Keren2015-03-301-1/+1
* Remove useMachineScheduler and replace it with subtarget optionsEric Christopher2015-03-111-0/+10
* [Hexagon] Removing more V4 predicates since V4 is the required minimum.Colin LeMahieu2015-02-091-6/+1
* Cache and use the subtarget that owns the target lowering.Eric Christopher2015-02-021-1/+1
* Move DataLayout back to the TargetMachine from TargetSubtargetInfoEric Christopher2015-01-261-2/+1
* Move all of the hexagon subtarget dependent variables from the targetEric Christopher2014-06-271-4/+11
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