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* [Hexagon] Reapplying 224775 load words.Colin LeMahieu2014-12-231-1/+1
| | | | llvm-svn: 224786
* Reverting 224775 until mayLoad flag is addressed.Colin LeMahieu2014-12-231-1/+1
| | | | llvm-svn: 224783
* [Hexagon] Adding word loads.Colin LeMahieu2014-12-231-1/+1
| | | | llvm-svn: 224775
* [Hexagon] Adding signed halfword loads.Colin LeMahieu2014-12-231-1/+1
| | | | llvm-svn: 224774
* [Hexagon] Adding unsigned halfword load.Colin LeMahieu2014-12-231-1/+1
| | | | llvm-svn: 224772
* [Hexagon] Adding memb instruction. Fixing whitespace in test from 224730.Colin LeMahieu2014-12-221-1/+1
| | | | llvm-svn: 224735
* [Hexagon] Adding classes and load unsigned byte instruction, updating usages.Colin LeMahieu2014-12-221-1/+1
| | | | llvm-svn: 224730
* [Hexagon] Converting from ADD_rr to A2_add which has encoding bits.Colin LeMahieu2014-11-181-4/+4
| | | | | | Adding test to show correct instruction selection and encoding. llvm-svn: 222249
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-6/+3
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-3/+6
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* Make consistent use of MCPhysReg instead of uint16_t throughout the tree.Craig Topper2014-04-041-5/+4
| | | | llvm-svn: 205610
* Re-sort all of the includes with ./utils/sort_includes.py so thatChandler Carruth2014-01-071-5/+5
| | | | | | | | | | subsequent changes are easier to review. About to fix some layering issues, and wanted to separate out the necessary churn. Also comment and sink the include of "Windows.h" in three .inc files to match the usage in Memory.inc. llvm-svn: 198685
* Remove getEHExceptionRegister and getEHHandlerRegister.Rafael Espindola2013-10-071-8/+0
| | | | | | They haven't been used for a long time. Patch by MathOnNapkins. llvm-svn: 192099
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-4/+4
| | | | | | the internals of TargetMachine could change. llvm-svn: 183490
* Remove unused function.Rafael Espindola2013-05-101-10/+0
| | | | llvm-svn: 181606
* Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and ↵Jyotsna Verma2013-03-221-26/+40
| | | | | | word. llvm-svn: 177747
* Remove code copied from GenRegisterInfo.inc.Andrew Trick2013-02-221-52/+0
| | | | | | | | There's no apparent reason this code was copied from generated source into a .cpp. It sets a bad example for those working on other targets and trying to understand the register info API. llvm-svn: 175849
* Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky2013-02-211-15/+0
| | | | | | | | | | | | | | | to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. llvm-svn: 175788
* [PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier2013-01-311-27/+23
| | | | | | | Each target implementation was needlessly recomputing the index. Part of rdar://13076458 llvm-svn: 174083
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-2/+2
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-7/+7
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Porting Hexagon MI Scheduler to the new API.Sergei Larin2012-09-041-0/+52
| | | | | | | Change current Hexagon MI scheduler to use new converging scheduler. Integrates DFA resource model into it. llvm-svn: 163137
* Fix some uses of getSubRegisters() to use getSubReg() instead.Jakob Stoklund Olesen2012-05-301-1/+1
| | | | | | | It is better to address sub-registers directly by name instead of relying on their position in the sub-register list. llvm-svn: 157703
* Hexagon V5 FP Support.Sirish Pande2012-05-101-7/+14
| | | | llvm-svn: 156568
* Revert r155365, r155366, and r155367. All three of these have regressionChandler Carruth2012-04-231-14/+7
| | | | | | | | | | | test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. llvm-svn: 155372
* Hexagon V5 (floating point) support.Sirish Pande2012-04-231-7/+14
| | | | llvm-svn: 155367
* This reverts a long string of commits to the Hexagon backend. TheseChandler Carruth2012-04-181-14/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commits have had several major issues pointed out in review, and those issues are not being addressed in a timely fashion. Furthermore, this was all committed leading up to the v3.1 branch, and we don't need piles of code with outstanding issues in the branch. It is possible that not all of these commits were necessary to revert to get us back to a green state, but I'm going to let the Hexagon maintainer sort that out. They can recommit, in order, after addressing the feedback. Reverted commits, with some notes: Primary commit r154616: HexagonPacketizer - There are lots of review comments here. This is the primary reason for reverting. In particular, it introduced large amount of warnings due to a bad construct in tablegen. - Follow-up commits that should be folded back into this when reposting: - r154622: CMake fixes - r154660: Fix numerous build warnings in release builds. - Please don't resubmit this until the three commits above are included, and the issues in review addressed. Primary commit r154695: Pass to replace transfer/copy ... - Reverted to minimize merge conflicts. I'm not aware of specific issues with this patch. Primary commit r154703: New Value Jump. - Primarily reverted due to merge conflicts. - Follow-up commits that should be folded back into this when reposting: - r154703: Remove iostream usage - r154758: Fix CMake builds - r154759: Fix build warnings in release builds - Please incorporate these fixes and and review feedback before resubmitting. Primary commit r154829: Hexagon V5 (floating point) support. - Primarily reverted due to merge conflicts. - Follow-up commits that should be folded back into this when reposting: - r154841: Remove unused variable (fixing build warnings) There are also accompanying Clang commits that will be reverted for consistency. llvm-svn: 155047
* Hexagon V5 (Floating Point) Support.Sirish Pande2012-04-161-7/+14
| | | | llvm-svn: 154829
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-1/+1
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-041-4/+4
| | | | | | size of static data. llvm-svn: 151996
* Efficient pattern for store truncate. Patch by Evandro Menezes.Sirish Pande2012-02-221-2/+1
| | | | llvm-svn: 151166
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-5/+3
| | | | llvm-svn: 149961
* Hexagon: Remove forbidden iostream includes (it introduces static initializers)Benjamin Kramer2012-02-061-9/+8
| | | | | | Reorder includes while at it. llvm-svn: 149863
* Clean up some Release build warnings.Benjamin Kramer2011-12-271-12/+8
| | | | llvm-svn: 147289
* Add MCTargetDesc library to Hexagon targetTony Linthicum2011-12-151-0/+1
| | | | llvm-svn: 146692
* Hexagon backend supportTony Linthicum2011-12-121-0/+322
llvm-svn: 146412
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