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* TargetLowering: Change isShuffleMaskLegal's mask argument type to ↵Zvi Rackover2017-07-261-2/+1
| | | | | | | | | | | | | ArrayRef<int>. NFCI. Changing mask argument type from const SmallVectorImpl<int>& to ArrayRef<int>. This came up in D35700 where a mask is received as an ArrayRef<int> and we want to pass it to TargetLowering::isShuffleMaskLegal(). Also saves a few lines of code. llvm-svn: 309085
* [SystemZ, LoopStrengthReduce]Jonas Paulsson2017-07-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes LSR generate better code for SystemZ in the cases of memory intrinsics, Load->Store pairs or comparison of immediate with memory. In order to achieve this, the following common code changes were made: * New TTI hook: LSRWithInstrQueries(), which defaults to false. Controls if LSR should do instruction-based addressing evaluations by calling isLegalAddressingMode() with the Instruction pointers. * In LoopStrengthReduce: handle address operands of memset, memmove and memcpy as address uses, and call isFoldableMemAccessOffset() for any LSRUse::Address, not just loads or stores. SystemZ changes: * isLSRCostLess() implemented with Insns first, and without ImmCost. * New function supportedAddressingMode() that is a helper for TTI methods looking at Instructions passed via pointers. Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D35262 https://reviews.llvm.org/D35049 llvm-svn: 308729
* [Hexagon] Remove custom lowering of loads of v4i16Krzysztof Parzyszek2017-07-171-1/+0
| | | | | | | The target-independent lowering works fine, except concatenating 32-bit words. Add a pattern to generate A2_combinew instead of 64-bit asl/or. llvm-svn: 308186
* [Hexagon] Replace ISD opcode VPACK with VPACKE/VPACKO, NFCKrzysztof Parzyszek2017-07-141-1/+2
| | | | | | This breaks up pack-even and pack-odd into two separate operations. llvm-svn: 308049
* [Hexagon] Convert typed ISD opcodes to generic ones, NFCKrzysztof Parzyszek2017-07-101-8/+4
| | | | llvm-svn: 307582
* [Hexagon] Remove unused ISD opcodes, NFCKrzysztof Parzyszek2017-07-101-15/+0
| | | | llvm-svn: 307580
* DAG: Make mayBeEmittedAsTailCall parameter constMatt Arsenault2017-04-181-1/+1
| | | | llvm-svn: 300603
* [Hexagon] Implement HexagonTargetLowering::CanLowerReturnKrzysztof Parzyszek2017-04-131-0/+5
| | | | | | | | Patch by Michael Wu. Differential Revision: https://reviews.llvm.org/D32000 llvm-svn: 300199
* [Hexagon] Patterns for CTPOP, BSWAP and BITREVERSEKrzysztof Parzyszek2017-02-231-2/+0
| | | | llvm-svn: 295981
* [Hexagon] Implement @llvm.readcyclecounter()Krzysztof Parzyszek2017-02-221-0/+2
| | | | llvm-svn: 295892
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-171-1/+1
| | | | | | Reapply r295371 with a fix for the Windows bot failures. llvm-svn: 295504
* Revert "[Hexagon] Start using regmasks on calls"Rafael Espindola2017-02-171-1/+1
| | | | | | | | | | This reverts commit r295371. It broke windows bots: http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/11402/steps/test-llvm/logs/stdio llvm-svn: 295402
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-161-1/+1
| | | | | | All the cool targets are doing it... llvm-svn: 295371
* [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2016-12-171-6/+18
| | | | | | other minor fixes (NFC). llvm-svn: 290024
* [Hexagon] Relocate pattern-related bits to proper placesKrzysztof Parzyszek2016-11-051-4/+0
| | | | llvm-svn: 286049
* [Hexagon] Better handling of HVX vector loweringKrzysztof Parzyszek2016-09-131-0/+3
| | | | | | | - Expand SELECT_CC and BR_CC for vector types. - Implement TLI::isShuffleMaskLegal. llvm-svn: 281397
* [Hexagon] Do not cache alloca instructions during iselKrzysztof Parzyszek2016-08-191-3/+0
| | | | | | | | They can be deleted or replicated, so the cache may become outdated. They only need to be visited once during frame lowering, so just scan the function instead. llvm-svn: 279297
* [Hexagon] Improvements to handling and generation of FP instructionsKrzysztof Parzyszek2016-08-191-0/+6
| | | | | | | | | Improved handling of fma, floating point min/max, additional load/store instructions for floating point types. Patch by Jyotsna Verma. llvm-svn: 279239
* [Hexagon] Standardize pseudo-instructions for calls and returnsKrzysztof Parzyszek2016-08-121-2/+2
| | | | | | | | | | | | | | | | | | | - CALLv3nr PS_call_nr - CALLRv3nr PS_callr_nr - CALLstk PS_call_stk - TCRETURNi PS_tailcall_i - TCRETURNr PS_tailcall_r - JMPret PS_jmpret - JMPrett PS_jmprett - JMPretf PS_jmpretf - JMPrettnew PS_jmprettnew - JMPretfnew PS_jmpretfnew - JMPrettnewpt PS_jmprettnewpt - JMPretfnewpt PS_jmpretfnewpt llvm-svn: 278499
* [Hexagon] Remove unneeded/unused ISD opcodes ARGEXTEND and FCONST32Krzysztof Parzyszek2016-08-101-2/+0
| | | | llvm-svn: 278236
* [Hexagon] Improvements to address mode checks in TargetLoweringKrzysztof Parzyszek2016-08-021-0/+4
| | | | | | | - Implement getOptimalMemOpType. - Check BaseOffset in isLegalAddressingMode. llvm-svn: 277494
* [Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVXKrzysztof Parzyszek2016-07-291-0/+4
| | | | | | | | | | | | | | | | If the mask of a vector shuffle has alternating odd or even numbers starting with 1 or 0 respectively up to the largest possible index for the given type in the given HVX mode (single of double) we can generate vpacko or vpacke instruction respectively. E.g. %42 = shufflevector <32 x i16> %37, <32 x i16> %41, <32 x i32> <i32 1, i32 3, ..., i32 63> is %42.h = vpacko(%41.w, %37.w) Patch by Pranav Bhandarkar. llvm-svn: 277168
* CodeGen: Use MachineInstr& in TargetLowering, NFCDuncan P. N. Exon Smith2016-06-301-2/+3
| | | | | | | | | | | | | This is a mechanical change to make TargetLowering API take MachineInstr& (instead of MachineInstr*), since the argument is expected to be a valid MachineInstr. In one case, changed a parameter from MachineInstr* to MachineBasicBlock::iterator, since it was used as an insertion point. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. llvm-svn: 274287
* [Hexagon] Handle expansion of cmpxchgKrzysztof Parzyszek2016-06-221-0/+2
| | | | llvm-svn: 273432
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-121-11/+15
| | | | | | | | This used to be free, copying and moving DebugLocs became expensive after the metadata rewrite. Passing by reference eliminates a ton of track/untrack operations. No functionality change intended. llvm-svn: 272512
* [Hexagon] Recognize "q" and "v" in inline-asm as register constraintsKrzysztof Parzyszek2016-05-181-2/+2
| | | | llvm-svn: 269933
* Use MVT instead of EVT to remove a bunch of unnecessary calls to getSimpleVT.Craig Topper2016-04-151-1/+1
| | | | llvm-svn: 266414
* [Hexagon] Improve handling of unaligned vector loads and storesKrzysztof Parzyszek2016-03-281-0/+3
| | | | llvm-svn: 264584
* [Hexagon] Implement TLS supportKrzysztof Parzyszek2016-02-181-0/+10
| | | | | | Patch by Anand Kodnani. llvm-svn: 261218
* [Hexagon] Add support for __builtin_prefetchKrzysztof Parzyszek2016-02-181-0/+2
| | | | llvm-svn: 261210
* [Hexagon] Add PIC supportKrzysztof Parzyszek2015-12-181-5/+12
| | | | llvm-svn: 256025
* [Hexagon] Implement CONCAT_VECTORS for HVX using V6_vcombineKrzysztof Parzyszek2015-12-031-0/+1
| | | | llvm-svn: 254617
* [Hexagon] Lowering of V60/HVX vector typesKrzysztof Parzyszek2015-11-261-0/+5
| | | | llvm-svn: 254168
* [WinEH] Update exception pointer registersJoseph Tremoulet2015-11-071-0/+14
| | | | | | | | | | | | | | | | | | | | Summary: The CLR's personality routine passes these in rdx/edx, not rax/eax. Make getExceptionPointerRegister a virtual method parameterized by personality function to allow making this distinction. Similarly make getExceptionSelectorRegister a virtual method parameterized by personality function, for symmetry. Reviewers: pgavlin, majnemer, rnk Subscribers: jyknight, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14344 llvm-svn: 252383
* [CodeGen] Refactor TLI/AtomicExpand interface to make LLSC explicit.Ahmed Bougacha2015-09-111-4/+1
| | | | | | | | | | | | | | | We used to have this magic "hasLoadLinkedStoreConditional()" callback, which really meant two things: - expand cmpxchg (to ll/sc). - expand atomic loads using ll/sc (rather than cmpxchg). Remove it, and, instead, introduce explicit callbacks: - bool shouldExpandAtomicCmpXchgInIR(inst) - AtomicExpansionKind shouldExpandAtomicLoadInIR(inst) Differential Revision: http://reviews.llvm.org/D12557 llvm-svn: 247429
* [CodeGen] Rename AtomicRMWExpansionKind to AtomicExpansionKind.Ahmed Bougacha2015-09-111-3/+3
| | | | | | This lets us generalize its usage to the other atomic instructions. llvm-svn: 247428
* [Hexagon] Add support for atomic RMW operationsKrzysztof Parzyszek2015-07-091-0/+15
| | | | llvm-svn: 241804
* Make isLegalAddressingMode() taking DataLayout as an argumentMehdi Amini2015-07-091-2/+2
| | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, llvm-commits, rafael, yaron.keren Differential Revision: http://reviews.llvm.org/D11040 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241778
* Make TargetLowering::getPointerTy() taking DataLayout as an argumentMehdi Amini2015-07-091-1/+2
| | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, ted, yaron.keren, rafael, llvm-commits Differential Revision: http://reviews.llvm.org/D11028 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241775
* [TargetLowering] StringRefize asm constraint getters.Benjamin Kramer2015-07-051-4/+3
| | | | | | | | There is some functional change here because it changes target code from atoi(3) to StringRef::getAsInteger which has error checking. For valid constraints there should be no difference. llvm-svn: 241411
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-1/+1
| | | | | | Apparently, the style needs to be agreed upon first. llvm-svn: 240390
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-1/+1
| | | | | | | | | | | | | The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! llvm-svn: 240137
* Add address space argument to isLegalAddressingModeMatt Arsenault2015-06-011-1/+2
| | | | | | | | | | This is important because of different addressing modes depending on the address space for GPU targets. This only adds the argument, and does not update any of the uses to provide the correct address space. llvm-svn: 238723
* Change getTargetNodeName() to produce compiler warnings for missing cases, ↵Matthias Braun2015-05-071-1/+1
| | | | | | fix them llvm-svn: 236775
* [hexagon] Remove setHexLibcallName, it leaks memory.Benjamin Kramer2015-04-251-3/+0
| | | | | | | Just spell out the full names, it's not that much more code. No functional change intended. llvm-svn: 235801
* [Hexagon] Some cleanup of instruction selection codeKrzysztof Parzyszek2015-04-221-65/+42
| | | | llvm-svn: 235552
* [Hexagon] Overhaul of stack object allocationKrzysztof Parzyszek2015-04-221-1/+1
| | | | | | | | - Use static allocation for aligned stack objects. - Simplify dynamic stack object allocation. - Simplify elimination of frame-indices. llvm-svn: 235521
* [Hexagon] Add support for vector instructionsKrzysztof Parzyszek2015-03-191-17/+42
| | | | llvm-svn: 232728
* Re-commit: [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly ↵Daniel Sanders2015-03-171-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | memory constraints. Summary: But still handle them the same way since I don't know how they differ on this target. No functional change intended. Reviewers: kparzysz, adasgupt Reviewed By: kparzysz, adasgupt Subscribers: colinl, llvm-commits Differential Revision: http://reviews.llvm.org/D8204 Like for the PowerPC target, I've had to add 'i' to the constraint mappings in order to pass 2007-12-17-InvokeAsm.ll. It's not clear why 'i' has historically been treated as a memory constraint. llvm-svn: 232480
* Revert r232374: [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly ↵Daniel Sanders2015-03-161-5/+2
| | | | | | | | memory constraints. 2007-12-17-InvokeAsm.ll fails on the buildbot but not on my own system. Will investigate. llvm-svn: 232376
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