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* [CodeGen] Emit more precise AssertZext/AssertSext nodes.Eli Friedman2018-07-111-1/+1
| | | | | | | | | | | | This is marginally helpful for removing redundant extensions, and the code is easier to read, so it seems like an all-around win. In the new test i8-phi-ext.ll, we used to emit an AssertSext i8; now we emit an AssertZext i2, which allows the extension of the return value to be eliminated. Differential Revision: https://reviews.llvm.org/D49004 llvm-svn: 336868
* [Hexagon] Remove 'T' from HasVNN predicates, NFCKrzysztof Parzyszek2018-06-201-8/+8
| | | | | | Patch by Sumanth Gundapaneni. llvm-svn: 335124
* [DAGCombiner] Recognize more patterns for ABSKrzysztof Parzyszek2018-06-121-0/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D47831 llvm-svn: 334553
* [SelectionDAG] Provide default expansion for rotatesKrzysztof Parzyszek2018-06-121-0/+12
| | | | | | | | | | | | | Implement default legalization of rotates: either in terms of the rotation in the opposite direction (if legal), or in terms of shifts and ors. Implement generating of rotate instructions for Hexagon. Hexagon only supports rotates by an immediate value, so implement custom lowering of ROTL/ROTR on Hexagon. If a rotate is not legal, use the default expansion. Differential Revision: https://reviews.llvm.org/D47725 llvm-svn: 334497
* [Hexagon] Minor cleanups in isel loweringKrzysztof Parzyszek2018-06-051-9/+8
| | | | llvm-svn: 334015
* [SelectionDAG] Expand UADDO/USUBO into ADD/SUBCARRY if legal for targetKrzysztof Parzyszek2018-06-011-5/+32
| | | | | | | | | Additionally, implement handling of ADD/SUBCARRY on Hexagon, utilizing the UADDO/USUBO expansion. Differential Revision: https://reviews.llvm.org/D47559 llvm-svn: 333751
* Set ADDE/ADDC/SUBE/SUBC to expand by defaultAmaury Sechet2018-06-011-26/+3
| | | | | | | | | | | | | | | Summary: They've been deprecated in favor of UADDO/ADDCARRY or USUBO/SUBCARRY for a while. Target that uses these opcodes are changed in order to ensure their behavior doesn't change. Reviewers: efriedma, craig.topper, dblaikie, bkramer Subscribers: jholewinski, arsenm, jyknight, sdardis, nemanjai, nhaehnle, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, mgrang, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D47422 llvm-svn: 333748
* [Hexagon] Generate post-increment for floating point typesBrendon Cahoon2018-05-181-4/+5
| | | | | | | | | | The code that generates post-increments for Hexagon considered integer values only. This patch adds support to generate them for floating point values, f32 and f64. Differential Revision: https://reviews.llvm.org/D47036 llvm-svn: 332748
* [Hexagon] Add a target feature to control using small data sectionKrzysztof Parzyszek2018-05-141-1/+1
| | | | llvm-svn: 332292
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-5/+5
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* [Hexagon] Improve HVX instruction selection (bitcast, vsplat)Krzysztof Parzyszek2018-04-201-0/+1
| | | | | | | | | | There was some unfortunate interaction between VSPLAT and BITCAST related to the selection of constant vectors (coming from selecting shuffles). Introduce VSPLATW that always splats a 32-bit word, and can have arbitrary result type (to avoid BITCASTs of VSPLAT). Clean up the previous selection of BITCAST/VSPLAT. llvm-svn: 330471
* [Hexagon] Add/fix patterns for 32/64-bit vector compares and logical opsKrzysztof Parzyszek2018-04-191-47/+48
| | | | llvm-svn: 330330
* Fix a bunch of typoes. NFCFangrui Song2018-03-301-1/+1
| | | | llvm-svn: 328907
* [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to ↵Craig Topper2018-03-291-1/+1
| | | | | | | | | | | | CodeGen layer. Currently EVT is in the IR layer only because of Function.cpp needing a very small piece of the functionality of EVT::getEVTString(). The rest of EVT is used in codegen making CodeGen a better place for it. The previous code converted a Type* to EVT and then called getEVTString. This was only expected to handle the primitive types from Type*. Since there only a few primitive types, we can just print them as strings directly. Differential Revision: https://reviews.llvm.org/D45017 llvm-svn: 328806
* [Hexagon] Add support to handle bit-reverse load intrinsicsKrzysztof Parzyszek2018-03-291-0/+102
| | | | | | Patch by Sumanth Gundapaneni. llvm-svn: 328774
* Fix layering by moving ValueTypes.h from CodeGen to IRDavid Blaikie2018-03-231-1/+1
| | | | | | ValueTypes.h is implemented in IR already. llvm-svn: 328397
* HexagonISelLowering.cpp: fix 'enum in bool context' warningHans Wennborg2018-03-191-2/+2
| | | | llvm-svn: 327832
* [Hexagon] Fix zero-extending non-HVX bool vectorsKrzysztof Parzyszek2018-03-161-1/+8
| | | | llvm-svn: 327712
* [Hexagon] Ignore indexed loads when handling unaligned loadsKrzysztof Parzyszek2018-03-081-3/+4
| | | | llvm-svn: 327037
* [Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned onesKrzysztof Parzyszek2018-03-071-5/+106
| | | | | | | | | This is a follow-up to r325169, this time for all types, not just HVX vector types. Disable this by default, since it's not always safe. llvm-svn: 326915
* [Hexagon] Handle VACOPY in isel loweringKrzysztof Parzyszek2018-03-021-0/+1
| | | | llvm-svn: 326599
* Recommit [Hexagon] Make the vararg handling a bit more robustKrzysztof Parzyszek2018-02-151-19/+11
| | | | | | | Use the FunctionType of the callee when it's available. It may not be available for synthetic calls to functions specified by external symbols. llvm-svn: 325269
* Revert "[Hexagon] Make the vararg handling a bit more robust"Krzysztof Parzyszek2018-02-151-8/+19
| | | | | | This is breaking lit tests. llvm-svn: 325266
* [Hexagon] Make the vararg handling a bit more robustKrzysztof Parzyszek2018-02-151-19/+8
| | | | | | | The FunctionType of the callee is always available, even if the Function of the callee is not. Use that to get the number of fixed parameters. llvm-svn: 325259
* [Hexagon] Fix lowering of formal arguments after r324737Krzysztof Parzyszek2018-02-151-18/+16
| | | | | | Lowering of formal arguments needs to be aware of vararg functions. llvm-svn: 325255
* [Hexagon] Split HVX vector pair loads/stores, expand unaligned loadsKrzysztof Parzyszek2018-02-141-0/+11
| | | | llvm-svn: 325169
* [Hexagon] Simplify some code, NFCKrzysztof Parzyszek2018-02-131-114/+44
| | | | llvm-svn: 325014
* [Hexagon] Remove unnecessary checkKrzysztof Parzyszek2018-02-131-2/+0
| | | | llvm-svn: 325013
* [Hexagon] Express calling conventions via .td file instead of hand-codingKrzysztof Parzyszek2018-02-091-531/+119
| | | | | | Additionally, simplify the rest of the argument/parameter lowering code. llvm-svn: 324737
* [Hexagon] Extract HVX lowering and selection into HVX-specific files, NFCKrzysztof Parzyszek2018-02-061-230/+16
| | | | llvm-svn: 324392
* [Hexagon] Lower concat of more than 2 vectors into build_vectorKrzysztof Parzyszek2018-02-061-9/+9
| | | | llvm-svn: 324391
* [Hexagon] Split HVX operations on vector pairsKrzysztof Parzyszek2018-02-061-30/+52
| | | | | | | | Vector pairs are legal types, but not every operation can work on pairs. For those operations that are legal for single vectors, generate a concat of their results on pair halves. llvm-svn: 324350
* [Hexagon] Handle lowering of SETCC via setCondCodeActionKrzysztof Parzyszek2018-02-061-1/+10
| | | | | | | | | | It was expanded directly into instructions earlier. That was to avoid loads from a constant pool for a vector negation: "xor x, splat(i1 -1)". Implement ISD opcodes QTRUE and QFALSE to denote logical vectors of all true and all false values, and handle setcc with negations through selection patterns. llvm-svn: 324348
* [Hexagon] Rename HexagonISelLowering::getNode to getInstr, NFCKrzysztof Parzyszek2018-01-311-21/+21
| | | | llvm-svn: 323916
* [Hexagon] Implement HVX codegen for vector shiftsKrzysztof Parzyszek2018-01-311-63/+29
| | | | llvm-svn: 323914
* [Hexagon] Handle ANY_EXTEND_VECTOR_INREG in loweringKrzysztof Parzyszek2018-01-311-0/+4
| | | | llvm-svn: 323912
* [Hexagon] Handle SETCC on vector pairs in loweringKrzysztof Parzyszek2018-01-311-0/+3
| | | | llvm-svn: 323911
* Revert: [Hexagon] Make sure that offset on globals matches alignment ↵Krzysztof Parzyszek2018-01-301-40/+14
| | | | | | | | | | | | | requirements This reverts r323562, since it wasn't actually necessary. Constant- extended offsets do not need to be aligned, as long as the effective address is aligned. Keep the testcase, with a modification which checks that such offsets are not unnecessarily avoided. llvm-svn: 323798
* [Hexagon] Make sure that offset on globals matches alignment requirementsKrzysztof Parzyszek2018-01-261-14/+40
| | | | | | | | | | | | | A correctly aligned address may happen to be separated into a variable part and a constant part, where the constant part does not match the alignment needed in a load/store that uses this address. Such a constant cannot be used as an immediate offset in an indexed instruction. When lowering a global address, make sure that if there is an offset folded into the global, the offset is valid for all uses in load/store instructions. llvm-svn: 323562
* [Hexagon] SETEQ and SETNE are valid integer condition codesKrzysztof Parzyszek2018-01-251-1/+2
| | | | llvm-svn: 323452
* [Hexagon] Remove unused HexagonISD opcodes, NFCKrzysztof Parzyszek2018-01-241-3/+0
| | | | llvm-svn: 323324
* Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.Simon Pilgrim2018-01-231-1/+1
| | | | llvm-svn: 323258
* [Hexagon] Implement basic vector operations on vectors vNi1Krzysztof Parzyszek2018-01-231-22/+278
| | | | | | | | | | | In addition to that, make sure that there are no boolean vector types that are associated with multiple register classes. Specifically, remove v32i1 and v64i1 from integer register classes. These types will correspond to results of vector comparisons, and as such should belong to the vector predicate class. Having them in scalar registers as well makes legalization ambiguous. llvm-svn: 323229
* [Hexagon] Implement signed and unsigned multiply-high for vectorsKrzysztof Parzyszek2018-01-151-0/+7
| | | | llvm-svn: 322499
* [Hexagon] Rewrite LowerVECTOR_SHUFFLE for 32-/64-bit vectorsKrzysztof Parzyszek2018-01-151-38/+115
| | | | | | | The old implementation was not always correct. The new one recognizes more shuffles that match specific instructions. llvm-svn: 322498
* [Hexagon] Fix building 64-bit vector from constant valuesKrzysztof Parzyszek2018-01-111-1/+1
| | | | | | The constants were aggregated in a reverse order. llvm-svn: 322303
* [Hexagon] Cast elements to correct type when creating constant vectorKrzysztof Parzyszek2018-01-111-1/+2
| | | | llvm-svn: 322301
* [Hexagon] Set boolean contents in HexagonISelLoweringKrzysztof Parzyszek2018-01-051-0/+2
| | | | llvm-svn: 321891
* [Hexagon] Replace INSERTRP/EXTRACTRP with INSERT/EXTRACT in HexagonISDKrzysztof Parzyszek2018-01-041-12/+4
| | | | llvm-svn: 321798
* [Hexagon] Allow construction of HVX vector predicatesKrzysztof Parzyszek2017-12-201-129/+203
| | | | | | Handle BUILD_VECTOR of boolean values. llvm-svn: 321220
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