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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-01-23 21:22:16 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-01-23 21:22:16 +0000 |
| commit | c1e2290d373b461f71744ad0792e8306a66f0dee (patch) | |
| tree | defcc6363f3eafa9cdce2b46f870643df8a6c8c0 /llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | |
| parent | 93a8b19d8c03b00bdfa5afc78f73fa2b17f5d285 (diff) | |
| download | bcm5719-llvm-c1e2290d373b461f71744ad0792e8306a66f0dee.tar.gz bcm5719-llvm-c1e2290d373b461f71744ad0792e8306a66f0dee.zip | |
Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.
llvm-svn: 323258
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index f7014088bba..caa45d0fb0c 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -3038,7 +3038,7 @@ HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { // Always produce 8 bits, repeat inputs if necessary. unsigned Rep = 8 / VecTy.getVectorNumElements(); for (unsigned i = 0; i != 8; ++i) { - SDValue S = DAG.getConstant(1 << i, dl, MVT::i32); + SDValue S = DAG.getConstant(1ull << i, dl, MVT::i32); Rs[i] = DAG.getSelect(dl, MVT::i32, Ops[i/Rep], S, Z); } for (ArrayRef<SDValue> A(Rs); A.size() != 1; A = A.drop_back(A.size()/2)) { |
