summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* Hexagon: Use multiclass for Jump instructions.Jyotsna Verma2013-05-011-2/+30
| | | | llvm-svn: 180885
* Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.Tim Northover2013-04-201-10/+0
| | | | llvm-svn: 179939
* Hexagon: Expand br_cc.Jyotsna Verma2013-04-041-0/+2
| | | | | | | | | | | | | It fixes following tests for Hexagon: CodeGen/Generic/2003-07-29-BadConstSbyte.ll CodeGen/Generic/2005-10-21-longlonggtu.ll CodeGen/Generic/2009-04-28-i128-cmp-crash.ll CodeGen/Generic/MachineBranchProb.ll CodeGen/Generic/builtin-expect.ll CodeGen/Generic/pr12507.ll llvm-svn: 178794
* DAGCombiner: Use correct value type for checking legality of BR_CC v3Tom Stellard2013-03-081-1/+3
| | | | | | | | | | | | | LegalizeDAG.cpp uses the value of the comparison operands when checking the legality of BR_CC, so DAGCombiner should do the same. v2: - Expand more BR_CC value types for NVPTX v3: - Expand correct BR_CC value types for Hexagon, Mips, and XCore. llvm-svn: 176694
* Hexagon: Handle i8, i16 and i1 Var Args.Jyotsna Verma2013-03-071-0/+10
| | | | llvm-svn: 176647
* Hexagon: Add support to lower block address.Jyotsna Verma2013-03-071-0/+12
| | | | llvm-svn: 176637
* reverting patch 176508.Jyotsna Verma2013-03-051-12/+0
| | | | llvm-svn: 176513
* Hexagon: Add support for lowering block address.Jyotsna Verma2013-03-051-0/+12
| | | | llvm-svn: 176508
* Hexagon: Expand addc, adde, subc and sube.Jyotsna Verma2013-03-051-0/+23
| | | | llvm-svn: 176505
* Hexagon: Expand cttz, ctlz, and ctpop for now.Anshuman Dasgupta2013-02-211-0/+5
| | | | llvm-svn: 175783
* Update TargetLowering ivars for name policy.Jim Grosbach2013-02-201-2/+2
| | | | | | | | | | | http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly ivars should be camel-case and start with an upper-case letter. A few in TargetLowering were starting with a lower-case letter. No functional change intended. llvm-svn: 175667
* Move MRI liveouts to Hexagon return instructions.Jakob Stoklund Olesen2013-02-051-10/+9
| | | | llvm-svn: 174407
* Teach SDISel to combine fsin / fcos into a fsincos node if the followingEvan Cheng2013-01-291-0/+2
| | | | | | | | | | | | | | | | | | conditions are met: 1. They share the same operand and are in the same BB. 2. Both outputs are used. 3. The target has a native instruction that maps to ISD::FSINCOS node or the target provides a sincos library call. Implemented the generic optimization in sdisel and enabled it for Mac OSX. Also added an additional optimization for x86_64 Mac OSX by using an alternative entry point __sincos_stret which returns the two results in xmm0 / xmm1. rdar://13087969 PR13204 llvm-svn: 173755
* Improve r172468: const_cast is not needed hereDmitri Gribenko2013-01-141-3/+2
| | | | llvm-svn: 172483
* Fix Another CastDavid Greene2013-01-141-1/+2
| | | | | | Properly cast code to eliminate cast-away-const errors. llvm-svn: 172468
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-7/+7
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-8/+8
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Finish the renaming.Rafael Espindola2012-11-211-1/+1
| | | | llvm-svn: 168437
* TargetLowering interface to set/get minimum block entries for jump tables.Sebastian Pop2012-09-251-0/+2
| | | | | | | | | | | | | | Provide interface in TargetLowering to set or get the minimum number of basic blocks whereby jump tables are generated for switch statements rather than an if sequence. getMinimumJumpTableEntries() defaults to 4. setMinimumJumpTableEntries() allows target configuration. This patch changes the default for the Hexagon architecture to 5 as it improves performance on some benchmarks. llvm-svn: 164628
* Remove tabs.Bill Wendling2012-07-191-4/+4
| | | | llvm-svn: 160477
* Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer2012-06-021-2/+2
| | | | llvm-svn: 157885
* Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCallJustin Holewinski2012-05-251-7/+11
| | | | | | | | | | to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB llvm-svn: 157479
* Hexagon V5 FP Support.Sirish Pande2012-05-101-118/+246
| | | | llvm-svn: 156568
* Revert r155365, r155366, and r155367. All three of these have regressionChandler Carruth2012-04-231-246/+118
| | | | | | | | | | | test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. llvm-svn: 155372
* Hexagon V5 (floating point) support.Sirish Pande2012-04-231-118/+246
| | | | llvm-svn: 155367
* llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build ↵NAKAMURA Takumi2012-04-211-0/+1
| | | | | | | | on MSVC. Thanks to Andy Gibbs, to report the issue. llvm-svn: 155287
* HexagonISelLowering.cpp: Reorder #includes.NAKAMURA Takumi2012-04-211-1/+2
| | | | llvm-svn: 155286
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-7/+7
| | | | | | since they are equivalent. llvm-svn: 155188
* This reverts a long string of commits to the Hexagon backend. TheseChandler Carruth2012-04-181-248/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commits have had several major issues pointed out in review, and those issues are not being addressed in a timely fashion. Furthermore, this was all committed leading up to the v3.1 branch, and we don't need piles of code with outstanding issues in the branch. It is possible that not all of these commits were necessary to revert to get us back to a green state, but I'm going to let the Hexagon maintainer sort that out. They can recommit, in order, after addressing the feedback. Reverted commits, with some notes: Primary commit r154616: HexagonPacketizer - There are lots of review comments here. This is the primary reason for reverting. In particular, it introduced large amount of warnings due to a bad construct in tablegen. - Follow-up commits that should be folded back into this when reposting: - r154622: CMake fixes - r154660: Fix numerous build warnings in release builds. - Please don't resubmit this until the three commits above are included, and the issues in review addressed. Primary commit r154695: Pass to replace transfer/copy ... - Reverted to minimize merge conflicts. I'm not aware of specific issues with this patch. Primary commit r154703: New Value Jump. - Primarily reverted due to merge conflicts. - Follow-up commits that should be folded back into this when reposting: - r154703: Remove iostream usage - r154758: Fix CMake builds - r154759: Fix build warnings in release builds - Please incorporate these fixes and and review feedback before resubmitting. Primary commit r154829: Hexagon V5 (floating point) support. - Primarily reverted due to merge conflicts. - Follow-up commits that should be folded back into this when reposting: - r154841: Remove unused variable (fixing build warnings) There are also accompanying Clang commits that will be reverted for consistency. llvm-svn: 155047
* Remove unused variableDavid Blaikie2012-04-161-1/+0
| | | | llvm-svn: 154841
* Hexagon V5 (Floating Point) Support.Sirish Pande2012-04-161-119/+249
| | | | llvm-svn: 154829
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-3/+2
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* Convert more static tables of registers used by calling convention to ↵Craig Topper2012-03-111-3/+3
| | | | | | uint16_t to reduce space. llvm-svn: 152538
* Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng2012-02-281-1/+1
| | | | | | direct call. llvm-svn: 151645
* Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar2012-02-281-1/+1
| | | | | | prediction. ...", it is breaking the Clang build during the Compiler-RT part. llvm-svn: 151630
* Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2012-02-281-1/+1
| | | | | | | | | | | | | | | | | the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 llvm-svn: 151623
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-8/+6
| | | | llvm-svn: 149961
* VLIW specific scheduler framework that utilizes deterministic finite ↵Andrew Trick2012-02-011-0/+1
| | | | | | | | | | automaton (DFA). This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling. Patch by Sergei Larin! llvm-svn: 149547
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-2/+0
| | | | llvm-svn: 148578
* Initializing to false makes better sense. Thanks, David.Chad Rosier2012-01-061-1/+1
| | | | llvm-svn: 147679
* Fix uninitialized variable warning.Chad Rosier2012-01-061-1/+1
| | | | llvm-svn: 147675
* Hexagon: Remove unused variables.Benjamin Kramer2011-12-181-5/+0
| | | | llvm-svn: 146846
* Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth2011-12-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | undefined result. This adds new ISD nodes for the new semantics, selecting them when the LLVM intrinsic indicates that the undef behavior is desired. The new nodes expand trivially to the old nodes, so targets don't actually need to do anything to support these new nodes besides indicating that they should be expanded. I've done this for all the operand types that I could figure out for all the targets. Owners of various targets, please review and let me know if any of these are incorrect. Note that the expand behavior is *conservatively correct*, and exactly matches LLVM's current behavior with these operations. Ideally this patch will not change behavior in any way. For example the regtest suite finds the exact same instruction sequences coming out of the code generator. That's why there are no new tests here -- all of this is being exercised by the existing test suite. Thanks to Duncan Sands for reviewing the various bits of this patch and helping me get the wrinkles ironed out with expanding for each target. Also thanks to Chris for clarifying through all the discussions that this is indeed the approach he was looking for. That said, there are likely still rough spots. Further review much appreciated. llvm-svn: 146466
* Hexagon backend supportTony Linthicum2011-12-121-0/+1503
llvm-svn: 146412
OpenPOWER on IntegriCloud