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* [Hexagon] Round 3 of selection pattern simplificationsKrzysztof Parzyszek2016-11-061-63/+0
| | | | | | | Remove unnecessary C++ functions for SDNode transforms. Move more pat frags to files where they are used. llvm-svn: 286077
* [Hexagon] Relocate pattern-related bits to proper placesKrzysztof Parzyszek2016-11-051-0/+14
| | | | llvm-svn: 286049
* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-011-1/+1
| | | | llvm-svn: 283004
* getVectorElementType().getSizeInBits() -> getScalarSizeInBits() ; NFCISanjay Patel2016-09-141-1/+1
| | | | llvm-svn: 281495
* [Hexagon] Fix subesthetic indentationKrzysztof Parzyszek2016-08-191-2/+2
| | | | llvm-svn: 279303
* [Hexagon] Standardize next batch of pseudo instructionsKrzysztof Parzyszek2016-08-161-18/+12
| | | | | | | | | | | | | ALIGNA PS_aligna ALLOCA PS_alloca TFR_FI PS_fi TFR_FIA PS_fia TFR_PdFalse PS_false TFR_PdTrue PS_true VMULW PS_vmulw VMULW_ACC PS_vmulw_acc llvm-svn: 278832
* [Hexagon] Use integer instructions for floating point immediatesKrzysztof Parzyszek2016-08-101-10/+6
| | | | | | | | | | | | Floating point instructions use general purpose registers, so the few instructions that can put floating point immediates into registers are, in fact, integer instruction. Use them explicitly instead of having pseudo-instructions specifically for dealing with floating point values. Simplify the constant loading instructions (from sdata) to have only two: one for 32-bit values and one for 64-bit values: CONST32 and CONST64. llvm-svn: 278244
* Move helpers into anonymous namespaces. NFC.Benjamin Kramer2016-08-061-0/+2
| | | | llvm-svn: 277916
* [Hexagon] Remove unused optionKrzysztof Parzyszek2016-08-021-7/+0
| | | | llvm-svn: 277496
* [Hexagon] Tidy up some code, NFC: reapply r277372 with a fixKrzysztof Parzyszek2016-08-011-96/+74
| | | | llvm-svn: 277383
* Revert r277372, it is causing buildbot failuresKrzysztof Parzyszek2016-08-011-72/+90
| | | | llvm-svn: 277374
* [Hexagon] Tidy up some code, NFCKrzysztof Parzyszek2016-08-011-90/+72
| | | | llvm-svn: 277372
* Fixed MSVC out of range shift warningSimon Pilgrim2016-07-291-1/+1
| | | | llvm-svn: 277195
* [Hexagon] Improve balancing of address calculationKrzysztof Parzyszek2016-07-291-3/+738
| | | | | | | | | Rebalances address calculation trees and applies Hexagon-specific optimizations to the trees to improve instruction selection. Patch by Tobias Edler von Koch. llvm-svn: 277151
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-281-9/+9
| | | | | | | getFrameInfo() never returns nullptr so we should use a reference instead of a pointer. llvm-svn: 277017
* [SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, ↵Justin Lebar2016-07-151-4/+4
| | | | | | | | | | | | | | | | | | | | | | | getStore, and friends. Summary: Instead, we take a single flags arg (a bitset). Also add a default 0 alignment, and change the order of arguments so the alignment comes before the flags. This greatly simplifies many callsites, and fixes a bug in AMDGPUISelLowering, wherein the order of the args to getLoad was inverted. It also greatly simplifies the process of adding another flag to getLoad. Reviewers: chandlerc, tstellarAMD Subscribers: jholewinski, arsenm, jyknight, dsanders, nemanjai, llvm-commits Differential Revision: http://reviews.llvm.org/D22249 llvm-svn: 275592
* [Hexagon] Improve patterns with stack-based addressingKrzysztof Parzyszek2016-07-151-0/+20
| | | | | | | | | - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
* [Hexagon] Equally-sized vectors are equivalent in ISel (except vNi1)Krzysztof Parzyszek2016-06-271-0/+21
| | | | llvm-svn: 273885
* [Hexagon] Simplify (+fix) instruction selection for indexed loads/storesKrzysztof Parzyszek2016-06-241-308/+161
| | | | llvm-svn: 273733
* Preserve DebugInfo when replacing values in DAGCombinerNirav Dave2016-06-231-2/+0
| | | | | | | | | | | | | | | | | | | | | Recommiting after correcting over-eager Debug Value transfer fixing PR28270. [DAG] Previously debug values would transfer debuginfo for the selected start node for a replacement which allows for debug to be dropped. Push debug value transfer to occur with node/value replacement in SelectionDAG, remove now extraneous transfers of debug values. This refixes PR9817 which was being incompletely checked in the testsuite. Reviewers: jyknight Subscribers: dblaikie, llvm-commits Differential Revision: http://reviews.llvm.org/D21037 llvm-svn: 273585
* Revert r273456, "Preserve DebugInfo when replacing values in DAGCombiner" as ↵Peter Collingbourne2016-06-231-0/+2
| | | | | | it caused pr28270. llvm-svn: 273518
* [Hexagon] Add SDAG preprocessing step to expose shifted addressing modesKrzysztof Parzyszek2016-06-221-1/+54
| | | | | | | | | | | Transform: (store ch addr (add x (add (shl y c) e))) to: (store ch addr (add x (shl (add y d) c))), where e = (shl d c) for some integer d. The purpose of this is to enable generation of loads/stores with shifted addressing mode, i.e. mem(x+y<<#c). For that, the shift value c must be 0, 1 or 2. llvm-svn: 273466
* Preserve DebugInfo when replacing values in DAGCombinerNirav Dave2016-06-221-2/+0
| | | | | | | | | | | | | | | | | | | | | Recommiting after fixing over-aggressive assertion [DAG] Previously debug values would transfer debuginfo for the selected start node for a replacement which allows for debug to be dropped. Push debug value transfer to occur with node/value replacement in SelectionDAG, remove now extraneous transfers of debug values. This refixes PR9817 which was being incompletely checked in the testsuite. Reviewers: jyknight Subscribers: dblaikie, llvm-commits Differential Revision: http://reviews.llvm.org/D21037 llvm-svn: 273456
* Revert "Preserve DebugInfo when replacing values in DAGCombiner"Nirav Dave2016-06-151-0/+2
| | | | | | | | | Reverting due to assertion failure in lib/CodeGen/SelectionDAG/InstrEmitter.cpp This reverts commit r272792. llvm-svn: 272799
* Preserve DebugInfo when replacing values in DAGCombinerNirav Dave2016-06-151-2/+0
| | | | | | | | | | | | | | | | | | | [DAG] Previously debug values would transfer debuginfo for the selected start node for a replacement which allows for debug to be dropped. Push debug value transfer to occur with node/value replacement in SelectionDAG, remove now extraneous transfers of debug values. This refixes PR9817 which was being incompletely checked in the testsuite. Reviewers: jyknight Subscribers: dblaikie, llvm-commits Differential Revision: http://reviews.llvm.org/D21037 llvm-svn: 272792
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-121-21/+21
| | | | | | | | This used to be free, copying and moving DebugLocs became expensive after the metadata rewrite. Passing by reference eliminates a ton of track/untrack operations. No functionality change intended. llvm-svn: 272512
* Avoid copies of std::strings and APInt/APFloats where we only read from itBenjamin Kramer2016-06-081-1/+1
| | | | | | | | As suggested by clang-tidy's performance-unnecessary-copy-initialization. This can easily hit lifetime issues, so I audited every change and ran the tests under asan, which came back clean. llvm-svn: 272126
* Remove bogus initialization of the PPC and Hexagon SelectionDAGISelChandler Carruth2016-06-031-19/+1
| | | | | | | | | | | | | | | | | subclasses. These are not passes proper. We don't support registering them, they can't be constructed with default arguments, and the ID is actually in a base class. Only these two targets even had any boiler plate to try to do this, and it had to be munged out of the INITIALIZE_PASS macros to work. What's worse, the boiler plate has rotted and the "name" of the pass is actually the description string now!!! =/ All of this is completely unnecessary. No other target bothers, and nothing breaks if you don't initialize them because CodeGen has an entirely separate initialization path that is somewhat more durable than relying on the implicit initialization the way the 'opt' tool does for registered passes. llvm-svn: 271650
* [Hexagon] Remove dead nodes from SelectionDAG to avoid cyclesKrzysztof Parzyszek2016-05-131-1/+2
| | | | | | | | Recent changes to the instruction selection code exposed a problem where a dead node was not removed on time. This node had both input and output chains, which lead to an apparent cycle. llvm-svn: 269458
* SDAG: Implement Select instead of SelectImpl in HexagonDAGToDAGISelJustin Bogner2016-05-121-139/+189
| | | | | | | | | | | | - Where we were returning a node before, call ReplaceNode instead. - Where we had already replaced all uses and we returned a node, just remove the dead node instead. - Where we would return null to fall back to another selector, rename the method to try* and return a bool for success. Part of llvm.org/pr26808. llvm-svn: 269358
* SDAG: Clean up a dangling node in HexagonISelDAGToDAG::SelectImplJustin Bogner2016-05-121-1/+1
| | | | | | | | | When we convert to the void Select interface, leaving unreferenced nodes around won't be allowed anymore. Part of llvm.org/pr26808. llvm-svn: 269355
* [Hexagon] Properly handle instruction selection of vsplat intrinsicsKrzysztof Parzyszek2016-05-121-2/+3
| | | | llvm-svn: 269312
* SDAG: Avoid relying on the return value of SelectCode in Hexagon. NFCJustin Bogner2016-05-101-3/+11
| | | | | | | | | | This is a bit of a spot fix for now. I'll try to fix this up more comprehensively soon. This is part of the work to have Select return void instead of an SDNode *, which is in turn part of llvm.org/pr26808. llvm-svn: 269112
* SDAG: Rename Select->SelectImpl and repurpose Select as returning voidJustin Bogner2016-05-051-2/+2
| | | | | | | | | | | | | | This is a step towards removing the rampant undefined behaviour in SelectionDAG, which is a part of llvm.org/PR26808. We rename SelectionDAGISel::Select to SelectImpl and update targets to match, and then change Select to return void and consolidate the sketchy behaviour we're trying to get away from there. Next, we'll update backends to implement `void Select(...)` instead of SelectImpl and eventually drop the base Select implementation. llvm-svn: 268693
* [NFC] Header cleanupMehdi Amini2016-04-181-2/+0
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* [Hexagon] Improve handling of unaligned vector loads and storesKrzysztof Parzyszek2016-03-281-16/+39
| | | | llvm-svn: 264584
* [Hexagon] Eliminate pseudo instructions for circ/brev loads and storesKrzysztof Parzyszek2016-02-121-204/+175
| | | | | | | | | We can generate the actual instructions from the intrinsics without the need for pseudo-instructions. Also, since the intrinsics have a side- effect in a form of a store, attempt to optimize away loads from the store location. llvm-svn: 260690
* [Hexagon] Lowering of V60/HVX vector typesKrzysztof Parzyszek2015-11-261-49/+91
| | | | llvm-svn: 254168
* [Hexagon] Remove the remnants of isConstExtProfitableKrzysztof Parzyszek2015-10-201-14/+0
| | | | llvm-svn: 250845
* Hexagon: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-201-1/+1
| | | | | | | | | | | | | | | | | | | There are two things out of the ordinary in this commit. First, I made a loop obviously "infinite" in HexagonInstrInfo.cpp. After checking if an instruction was at the beginning of a basic block (in which case, `break`), the loop decremented and checked the iterator for `nullptr` as the loop condition. This has never been possible (the prev pointers are always been circular, so even with the weird ilist/iplist implementation, this isn't been possible), so I removed the condition. Second, in HexagonAsmPrinter.cpp there was another case of comparing a `MachineBasicBlock::instr_iterator` against `MachineBasicBlock::end()` (which returns `MachineBasicBlock::iterator`). While not incorrect, it's fragile. I switched this to `::instr_end()`. All that said, no functionality change intended here. llvm-svn: 250778
* Use more foreach loops in SelectionDAG. NFCPete Cooper2015-07-141-2/+2
| | | | llvm-svn: 242249
* [Hexagon] Making intrinsic tests agnostic to register allocation. Narrowing ↵Colin LeMahieu2015-06-121-0/+15
| | | | | | intrinsic parameters to appropriate width. llvm-svn: 239634
* Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"Sergey Dmitrouk2015-04-281-48/+50
| | | | | | | | | | | | | | | | | | | | | | | | | [DebugInfo] Add debug locations to constant SD nodes This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235989
* Revert "[DebugInfo] Add debug locations to constant SD nodes"Daniel Jasper2015-04-281-50/+48
| | | | | | | This breaks a test: http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/23870 llvm-svn: 235987
* [DebugInfo] Add debug locations to constant SD nodesSergey Dmitrouk2015-04-281-48/+50
| | | | | | | | | | | | | | | | | | | | | | | This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235977
* [Hexagon] Overhaul of stack object allocationKrzysztof Parzyszek2015-04-221-5/+46
| | | | | | | | - Use static allocation for aligned stack objects. - Simplify dynamic stack object allocation. - Simplify elimination of frame-indices. llvm-svn: 235521
* [Hexagon] Pattern match a CTZ loop into a call to countTrailingZeros.Benjamin Kramer2015-03-251-4/+1
| | | | | | No functional change intended. llvm-svn: 233192
* Make the Hexagon ISelDAGToDAG pass set the subtarget dynamicallyEric Christopher2015-03-211-8/+15
| | | | | | on each runOnMachineFunction invocation. llvm-svn: 232874
* [Hexagon] Add support for vector instructionsKrzysztof Parzyszek2015-03-191-0/+30
| | | | llvm-svn: 232728
* [Hexagon] Use pseudo-instructions for true/false predicate valuesKrzysztof Parzyszek2015-03-181-22/+6
| | | | llvm-svn: 232657
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