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* [Hexagon] Fixes -Wrange-loop-analysis warningsMark de Wever2019-12-221-1/+1
| | | | | | This avoids new warnings due to D68912 adds -Wrange-loop-analysis to -Wall. Differential Revision: https://reviews.llvm.org/D71814
* Use MCRegister in MCRegisterInfo's interfacesDaniel Sanders2019-08-021-1/+2
| | | | | | | | | | | | | | | | | Summary: As part of this, define DenseMapInfo for MCRegister (and Register while I'm at it) Depends on D65599 Reviewers: arsenm Subscribers: MatzeB, qcolombet, jvesely, wdng, nhaehnle, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65605 llvm-svn: 367719
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to ↵Daniel Sanders2019-08-011-9/+9
| | | | | | llvm::Register as started by r367614. NFC llvm-svn: 367633
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen2018-05-091-1/+1
| | | | | | | | | | | | | | | | | | Because we create a new kind of debug instruction, DBG_LABEL, we need to check all passes which use isDebugValue() to check MachineInstr is debug instruction or not. When expelling debug instructions, we should expel both DBG_VALUE and DBG_LABEL. So, I create a new function, isDebugInstr(), in MachineInstr to check whether the MachineInstr is debug instruction or not. This patch has no new test case. I have run regression test and there is no difference in regression test. Differential Revision: https://reviews.llvm.org/D45342 Patch by Hsiangkai Wang. llvm-svn: 331844
* [Hexagon] Memoize instruction positions in BitTrackerKrzysztof Parzyszek2018-02-051-9/+13
| | | | llvm-svn: 324250
* [Hexagon] Remove recursion in visitUsesOf, replace with use queueKrzysztof Parzyszek2017-12-151-37/+82
| | | | | | | | | | | | | | | | This is primarily to reduce stack usage, but ordering the use queue according to the position in the code (earlier instructions visited before later ones) reduces the number of unnecessary bottoms due to visiting instructions out of order, e.g. %reg1 = copy %reg0 %reg2 = copy %reg0 %reg3 = and %reg1, %reg2 Here, reg3 should be known to be same as reg0-2, but if reg3 is evaluated after reg1 is updated, but before reg2 is updated, the two inputs to the and will appear different, causing reg3 to become bottom. llvm-svn: 320866
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-8/+7
| | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-301-8/+8
| | | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 llvm-svn: 319427
* [CodeGen] Rename functions PrintReg* to printReg*Francis Visoiu Mistrih2017-11-281-6/+6
| | | | | | | | | | | LLVM Coding Standards: Function names should be verb phrases (as they represent actions), and command-like function should be imperative. The name should be camel case, and start with a lower case letter (e.g. openFile() or isFoo()). Differential Revision: https://reviews.llvm.org/D40416 llvm-svn: 319168
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* [Hexagon] Rangify some loops, NFCKrzysztof Parzyszek2017-10-161-35/+23
| | | | | | Recommit r315763 with a fix. llvm-svn: 315925
* Revert r315763: "[Hexagon] Rangify some loops, NFC"Krzysztof Parzyszek2017-10-131-23/+35
| | | | | | Broke some builds (using libstdc++). llvm-svn: 315769
* [Hexagon] Rangify some loops, NFCKrzysztof Parzyszek2017-10-131-35/+23
| | | | llvm-svn: 315763
* [Hexagon] Better determination of register classes in bit trackerKrzysztof Parzyszek2017-09-251-12/+11
| | | | | | | | | | | Add two callbacks to MachineEvaluator, so that specific implementations can specify more details about register classes: - composeWithSubRegIndex(RC,Idx), to provide the register class for a register from RC used in conjunction with a subregister index Idx. - getPhysRegBitWidth(Reg), to provide the size in bits of the given physical register. llvm-svn: 314136
* [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-07-261-5/+8
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 309230
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-1/+1
| | | | | | | | | | | | | | | 1. RegisterClass::getSize() is split into two functions: - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const; - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const; 2. RegisterClass::getAlignment() is replaced by: - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const; This will allow making those values depend on subtarget features in the future. Differential Revision: https://reviews.llvm.org/D31783 llvm-svn: 301221
* [Hexagon] Cache reached blocks in bit tracker instead of scanning listKrzysztof Parzyszek2017-04-191-6/+4
| | | | llvm-svn: 300701
* [Hexagon] Allow setting register in BitVal without storing into mapKrzysztof Parzyszek2017-02-231-6/+10
| | | | | | | | | | | In the bit tracker, references to other bit values in which the register is 0 are prohibited. This means that generating self-referential register cells like { w:32 [0-15]:s[0-15] [16-31]:s[15] } is impossible. In order to get a self-referential cell, it had to be stored into a map and then reloaded from it. To avoid this step, add a function that will set the register to a given value without going through the map. llvm-svn: 296025
* [Hexagon, TableGen] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-01-041-53/+17
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 290925
* [Hexagon] Clear the flow queue after visiting a single instructionKrzysztof Parzyszek2016-09-131-0/+5
| | | | llvm-svn: 281339
* [Hexagon] Remove unnecessary llvm::, NFCKrzysztof Parzyszek2016-08-191-1/+1
| | | | llvm-svn: 279244
* [Hexagon-ish] Add function to print cell map contents in bit trackerKrzysztof Parzyszek2016-08-031-5/+8
| | | | llvm-svn: 277622
* [Hexagon] Rerun bit tracker on new instructions in RIEKrzysztof Parzyszek2016-07-261-0/+9
| | | | | | | | | | | | | | | | | | | Consider this case: vreg1 = A2_zxth vreg0 (1) ... vreg2 = A2_zxth vreg1 (2) Redundant instruction elimination could delete the instruction (1) because the user (2) only cares about the low 16 bits. Then it could delete (2) because the input is already zero-extended. The problem is that the properties allowing each individual instruction to be deleted depend on the existence of the other instruction, so either one can be deleted, but not both. The existing check for this situation in RIE was insufficient. The fix is to update all dependent cells when an instruction is removed (replaced via COPY) in RIE. llvm-svn: 276792
* Hexagon: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-121-43/+41
| | | | | | | | | | | | | | Avoid implicit iterator conversions from MachineInstrBundleIterator to MachineInstr* in the Hexagon backend, mostly by preferring MachineInstr& over MachineInstr* and switching to range-based for loops. There's a long tail of API cleanup here, but I'm planning to leave the rest to the Hexagon maintainers. HexagonInstrInfo defines many of its own predicates, and most of them still take MachineInstr*. Some of those actually check for nullptr, so I didn't feel comfortable changing them to MachineInstr& en masse. llvm-svn: 275142
* Avoid copies of std::strings and APInt/APFloats where we only read from itBenjamin Kramer2016-06-081-1/+1
| | | | | | | | As suggested by clang-tidy's performance-unnecessary-copy-initialization. This can easily hit lifetime issues, so I audited every change and ran the tests under asan, which came back clean. llvm-svn: 272126
* [Hexagon] Fix compilation error with GCC 6Krzysztof Parzyszek2016-02-181-66/+68
| | | | | | | | | | | | | | Compiling Hexagon target with GCC 6 produces "error: should have been declared inside" due to GCC PR c++/69657 which was merged. Properly wrapping operator<<() definitions within the namespace llvm fixes the issue. Author: domagoj.stolfa Differential Revision: http://reviews.llvm.org/D17281 llvm-svn: 261220
* ADT: Remove last implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-11-071-1/+1
| | | | | | | | | | Some implicit ilist iterator conversions have crept back into Analysis, Transforms, Hexagon, and llvm-stress. This removes them. I'll commit a patch immediately after this to disallow them (in a separate patch so that it's easy to revert if necessary). llvm-svn: 252371
* [Hexagon] Do not fall-through if there is no CFG edgeKrzysztof Parzyszek2015-10-201-1/+1
| | | | llvm-svn: 250850
* Hexagon: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-201-2/+2
| | | | | | | | | | | | | | | | | | | There are two things out of the ordinary in this commit. First, I made a loop obviously "infinite" in HexagonInstrInfo.cpp. After checking if an instruction was at the beginning of a basic block (in which case, `break`), the loop decremented and checked the iterator for `nullptr` as the loop condition. This has never been possible (the prev pointers are always been circular, so even with the weird ilist/iplist implementation, this isn't been possible), so I removed the condition. Second, in HexagonAsmPrinter.cpp there was another case of comparing a `MachineBasicBlock::instr_iterator` against `MachineBasicBlock::end()` (which returns `MachineBasicBlock::iterator`). While not incorrect, it's fragile. I switched this to `::instr_end()`. All that said, no functionality change intended here. llvm-svn: 250778
* [WinEH] Add some support for code generating catchpadReid Kleckner2015-08-271-1/+1
| | | | | | | We can now run 32-bit programs with empty catch bodies. The next step is to change PEI so that we get funclet prologues and epilogues. llvm-svn: 246235
* [Hexagon] Use composition instead of inheritance from STL typesBenjamin Kramer2015-07-181-2/+2
| | | | | | | | The standard containers are not designed to be inherited from, as illustrated by the MSVC hacks for NodeOrdering. No functional change intended. llvm-svn: 242616
* [Hexagon] Move BitTracker into the llvm namespace and remove redundant ↵Benjamin Kramer2015-07-131-9/+4
| | | | | | | | qualifications No functional change intended. llvm-svn: 242062
* [Hexagon] Fix unused variable warnings in NDEBUG build caused by r241595Krzysztof Parzyszek2015-07-071-6/+5
| | | | llvm-svn: 241600
* [Hexagon] Implement bit-tracking facility with specifics for HexagonKrzysztof Parzyszek2015-07-071-0/+1133
This includes code that is intended to be target-independent as well as the Hexagon-specific details. This is just the framework without any users. llvm-svn: 241595
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