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* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-232-134/+134
| | | | llvm-svn: 119990
* Fix a bug with extractelement on SPU.Kalle Raiskila2010-11-221-1/+1
| | | | | | | In the attached testcase, the element was never extracted (missing rotate). llvm-svn: 119973
* Move getInitialFrameState() to TargetFrameInfoAnton Korobeynikov2010-11-184-12/+10
| | | | llvm-svn: 119754
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-184-21/+15
| | | | llvm-svn: 119740
* Change CodeGen to use .loc directives. This produces a lot more readable outputRafael Espindola2010-11-181-2/+1
| | | | | | | | and testing is easier. A good example is the unknown-location.ll test that now can just look for ".loc 1 0 0". We also don't use a DW_LNE_set_address for every address change anymore. llvm-svn: 119613
* Improve code layout, mostly indentation. Kalle Raiskila2010-11-151-166/+150
| | | | | | No functionality change. llvm-svn: 119142
* Attempt to unbreak cmake-based buildsAnton Korobeynikov2010-11-151-0/+1
| | | | llvm-svn: 119098
* First step of huge frame-related refactoring: move emit{Prologue,Epilogue} ↵Anton Korobeynikov2010-11-155-224/+237
| | | | | | out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place llvm-svn: 119097
* move all the target's asmprinters into the main target. The piece Chris Lattner2010-11-145-27/+2
| | | | | | | that should be split out is the InstPrinter (if a target is mc'ized). This change makes all the targets be consistent. llvm-svn: 119056
* Fix memory access lowering on SPU, addingKalle Raiskila2010-11-124-115/+252
| | | | | | | | | | | | support for the case where alignment<value size. These cases were silently miscompiled before this patch. Now they are overly verbose -especially storing is- and any front-end should still avoid misaligned memory accesses as much as possible. The bit juggling algorithm added here probably has some room for improvement still. llvm-svn: 118889
* Simplify uses of MVT and EVT. An MVT can be compared directlyDuncan Sands2010-11-031-1/+1
| | | | | | | with a SimpleValueType, while an EVT supports equality and inequality comparisons with SimpleValueType. llvm-svn: 118169
* Inline asm multiple alternative constraints development phase 2 - improved ↵John Thompson2010-10-292-0/+38
| | | | | | basic logic, added initial platform support. llvm-svn: 117667
* Change v64 datalayout in SPU.Kalle Raiskila2010-10-261-1/+1
| | | | | | | | | | | | | | The SPU ABI does not mention v64, and all examples in C suggest v128 are treated similarily to arrays, we use array alignment for v64 too. This makes the alignment of e.g. [2 x <2 x i32>] behave "intuitively" and similar to as if the elements were e.g. i32s. This also makes an "unaligned store" test to be aligned, with different (but functionally equivalent) code generated. llvm-svn: 117360
* Improve lowering of sext to i128 on SPU.Kalle Raiskila2010-10-181-2/+7
| | | | | | | | The old algorithm inserted a 'rotqmbyi' instruction which was both redundant and wrong - it made shufb select bytes from the wrong end of the input quad. llvm-svn: 116701
* Add the missing cases to the type->registerclass conversion function.Kalle Raiskila2010-10-071-0/+14
| | | | llvm-svn: 115921
* Implement two virtual functions in SPUTargetLowering.Kalle Raiskila2010-10-072-0/+31
| | | | | | | | | | Before the implementation of isLegalAddressingMode, some rare cases of code were miscompiled if optimized with the LoopStrengthReduce pass. It is unclear (to me) if LSR is "allowed" to produce wrong code with a bad TargetLowering, or if the bug is elsewhere and this patch just hides it. llvm-svn: 115919
* Zap some redundant 'ori $?, $?, 0' from SPU.Kalle Raiskila2010-10-012-67/+7
| | | | | | | Also remove some code that died in the process. One now non-existant ori is checked for. llvm-svn: 115306
* Add support to model pipeline bypass / forwarding.Evan Cheng2010-09-281-1/+1
| | | | llvm-svn: 115005
* Removed a bunch of unnecessary target_link_libraries.Oscar Fuentes2010-09-281-2/+0
| | | | llvm-svn: 114999
* fix a long standing wart: all the ComplexPattern's were beingChris Lattner2010-09-211-4/+8
| | | | | | | | | | | passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. llvm-svn: 114471
* update a bunch of code to use the MachinePointerInfo version of getStore.Chris Lattner2010-09-211-3/+4
| | | | llvm-svn: 114461
* it's more elegant to put the "getConstantPool" andChris Lattner2010-09-212-4/+5
| | | | | | | | "getFixedStack" on the MachinePointerInfo class. While this isn't the problem I'm setting out to solve, it is the right way to eliminate PseudoSourceValue, so lets go with it. llvm-svn: 114406
* Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.Kalle Raiskila2010-09-163-238/+177
| | | | | | | | | | | | | This cleans up after the mess r108567 left in the CellSPU backend. ORCvt-instruction were used to reinterpret registers, and the ORs were then removed by isMoveInstr(). This patch now removes 350 instrucions of format: or $3, $3, $3 (from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is checked for. Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain. llvm-svn: 114074
* Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng2010-09-101-2/+2
| | | | | | | | | | | take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. llvm-svn: 113570
* Silence compiler warning.Kalle Raiskila2010-09-091-1/+1
| | | | llvm-svn: 113478
* Fix CellSPU vector shuffles, again.Kalle Raiskila2010-09-081-7/+7
| | | | | | Some cases of lowering to rotate were miscompiled. llvm-svn: 113355
* zap dead code.Chris Lattner2010-09-042-44/+1
| | | | llvm-svn: 113073
* Zap dead code.Benjamin Kramer2010-09-032-13/+0
| | | | llvm-svn: 112955
* Fix lowering of INSERT_VECTOR_ELT in SPU. Kalle Raiskila2010-08-291-3/+4
| | | | | | The IDX was treated as byte index, not element index. llvm-svn: 112422
* Simplify eliminateFrameIndex() interface back down now that PEI doesn't needJim Grosbach2010-08-262-6/+3
| | | | | | to try to re-use scavenged frame index reference registers. rdar://8277890 llvm-svn: 112241
* zap dead codeChris Lattner2010-08-251-34/+0
| | | | llvm-svn: 112073
* Fix SPU BE to use all the available return registers.Kalle Raiskila2010-08-241-34/+16
| | | | | | llc used to assert on the added testcase. llvm-svn: 111911
* Remove some dead code from SPU BE that remainedKalle Raiskila2010-08-243-26/+6
| | | | | | from 64bit vector support. llvm-svn: 111910
* Fix a bug with insertelement on SPU. Kalle Raiskila2010-08-181-6/+11
| | | | | | | The previous algorithm in LowerVECTOR_SHUFFLE didn't check all requirements for "monotonic" shuffles. llvm-svn: 111361
* Remove all traces of v2[i,f]32 on SPU. Kalle Raiskila2010-08-185-110/+4
| | | | | | | | The "half vectors" are now widened to full size by the legalizer. The only exception is in parameter passing, where half vectors are expanded. This causes changes to some dejagnu tests. llvm-svn: 111360
* Change SPU C calling convention to match that described in Kalle Raiskila2010-08-181-11/+12
| | | | | | | | "SPU Application Binary Interface Specification, v1.9" by IBM. Specifically: use r3-r74 to pass parameters and the return value. llvm-svn: 111358
* fix emacs language spec's, patch by Edmund Grimley-Evans!Chris Lattner2010-08-171-1/+1
| | | | llvm-svn: 111241
* Have SPU handle halfvec stores aligned by 8 bytes.Kalle Raiskila2010-08-095-9/+57
| | | | llvm-svn: 110576
* Make SPU backend handle insertelement and Kalle Raiskila2010-08-043-2/+12
| | | | | | store for "half vectors" llvm-svn: 110198
* More SPU v2f32 stuff added: insertelement and shuffle.Kalle Raiskila2010-08-022-0/+9
| | | | llvm-svn: 110038
* Add preliminary v2f32 support for SPU. Like with v2i32, we justKalle Raiskila2010-08-024-69/+81
| | | | | | | | duplicate the instructions and operate on half vectors. Also reorder code in SPUInstrInfo.td for better coherency. llvm-svn: 110037
* Add preliminary v2i32 support for SPU backend. As there are noKalle Raiskila2010-08-024-6/+49
| | | | | | | | | | such registers in SPU, this support boils down to "emulating" them by duplicating instructions on the general purpose registers. This adds the most basic operations on v2i32: passing parameters, addition, subtraction, multiplication and a few others. llvm-svn: 110035
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-162-148/+0
| | | | llvm-svn: 108567
* Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling2010-07-161-3/+3
| | | | | | thus is a much more meaningful name. llvm-svn: 108563
* Don't pass StringRef by reference.Benjamin Kramer2010-07-142-3/+3
| | | | llvm-svn: 108366
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-112-100/+0
| | | | | | | | The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. llvm-svn: 108099
* Replace copyRegToReg with copyPhysReg for CellSPU.Jakob Stoklund Olesen2010-07-112-34/+10
| | | | llvm-svn: 108084
* Switch SPU calling convention (function arguments) Kalle Raiskila2010-07-084-118/+52
| | | | | | to a Tablegen implementation. llvm-svn: 107913
* Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman2010-07-072-2/+6
| | | | | | code can do calling-convention queries. This obviates OutputArgReg. llvm-svn: 107786
* Propagate debug loc.Devang Patel2010-07-061-2/+3
| | | | llvm-svn: 107710
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