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* Zap some redundant 'ori $?, $?, 0' from SPU.Kalle Raiskila2010-10-012-67/+7
| | | | | | | Also remove some code that died in the process. One now non-existant ori is checked for. llvm-svn: 115306
* Add support to model pipeline bypass / forwarding.Evan Cheng2010-09-281-1/+1
| | | | llvm-svn: 115005
* Removed a bunch of unnecessary target_link_libraries.Oscar Fuentes2010-09-281-2/+0
| | | | llvm-svn: 114999
* fix a long standing wart: all the ComplexPattern's were beingChris Lattner2010-09-211-4/+8
| | | | | | | | | | | passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. llvm-svn: 114471
* update a bunch of code to use the MachinePointerInfo version of getStore.Chris Lattner2010-09-211-3/+4
| | | | llvm-svn: 114461
* it's more elegant to put the "getConstantPool" andChris Lattner2010-09-212-4/+5
| | | | | | | | "getFixedStack" on the MachinePointerInfo class. While this isn't the problem I'm setting out to solve, it is the right way to eliminate PseudoSourceValue, so lets go with it. llvm-svn: 114406
* Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.Kalle Raiskila2010-09-163-238/+177
| | | | | | | | | | | | | This cleans up after the mess r108567 left in the CellSPU backend. ORCvt-instruction were used to reinterpret registers, and the ORs were then removed by isMoveInstr(). This patch now removes 350 instrucions of format: or $3, $3, $3 (from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is checked for. Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain. llvm-svn: 114074
* Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng2010-09-101-2/+2
| | | | | | | | | | | take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. llvm-svn: 113570
* Silence compiler warning.Kalle Raiskila2010-09-091-1/+1
| | | | llvm-svn: 113478
* Fix CellSPU vector shuffles, again.Kalle Raiskila2010-09-081-7/+7
| | | | | | Some cases of lowering to rotate were miscompiled. llvm-svn: 113355
* zap dead code.Chris Lattner2010-09-042-44/+1
| | | | llvm-svn: 113073
* Zap dead code.Benjamin Kramer2010-09-032-13/+0
| | | | llvm-svn: 112955
* Fix lowering of INSERT_VECTOR_ELT in SPU. Kalle Raiskila2010-08-291-3/+4
| | | | | | The IDX was treated as byte index, not element index. llvm-svn: 112422
* Simplify eliminateFrameIndex() interface back down now that PEI doesn't needJim Grosbach2010-08-262-6/+3
| | | | | | to try to re-use scavenged frame index reference registers. rdar://8277890 llvm-svn: 112241
* zap dead codeChris Lattner2010-08-251-34/+0
| | | | llvm-svn: 112073
* Fix SPU BE to use all the available return registers.Kalle Raiskila2010-08-241-34/+16
| | | | | | llc used to assert on the added testcase. llvm-svn: 111911
* Remove some dead code from SPU BE that remainedKalle Raiskila2010-08-243-26/+6
| | | | | | from 64bit vector support. llvm-svn: 111910
* Fix a bug with insertelement on SPU. Kalle Raiskila2010-08-181-6/+11
| | | | | | | The previous algorithm in LowerVECTOR_SHUFFLE didn't check all requirements for "monotonic" shuffles. llvm-svn: 111361
* Remove all traces of v2[i,f]32 on SPU. Kalle Raiskila2010-08-185-110/+4
| | | | | | | | The "half vectors" are now widened to full size by the legalizer. The only exception is in parameter passing, where half vectors are expanded. This causes changes to some dejagnu tests. llvm-svn: 111360
* Change SPU C calling convention to match that described in Kalle Raiskila2010-08-181-11/+12
| | | | | | | | "SPU Application Binary Interface Specification, v1.9" by IBM. Specifically: use r3-r74 to pass parameters and the return value. llvm-svn: 111358
* fix emacs language spec's, patch by Edmund Grimley-Evans!Chris Lattner2010-08-171-1/+1
| | | | llvm-svn: 111241
* Have SPU handle halfvec stores aligned by 8 bytes.Kalle Raiskila2010-08-095-9/+57
| | | | llvm-svn: 110576
* Make SPU backend handle insertelement and Kalle Raiskila2010-08-043-2/+12
| | | | | | store for "half vectors" llvm-svn: 110198
* More SPU v2f32 stuff added: insertelement and shuffle.Kalle Raiskila2010-08-022-0/+9
| | | | llvm-svn: 110038
* Add preliminary v2f32 support for SPU. Like with v2i32, we justKalle Raiskila2010-08-024-69/+81
| | | | | | | | duplicate the instructions and operate on half vectors. Also reorder code in SPUInstrInfo.td for better coherency. llvm-svn: 110037
* Add preliminary v2i32 support for SPU backend. As there are noKalle Raiskila2010-08-024-6/+49
| | | | | | | | | | such registers in SPU, this support boils down to "emulating" them by duplicating instructions on the general purpose registers. This adds the most basic operations on v2i32: passing parameters, addition, subtraction, multiplication and a few others. llvm-svn: 110035
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-162-148/+0
| | | | llvm-svn: 108567
* Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling2010-07-161-3/+3
| | | | | | thus is a much more meaningful name. llvm-svn: 108563
* Don't pass StringRef by reference.Benjamin Kramer2010-07-142-3/+3
| | | | llvm-svn: 108366
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-112-100/+0
| | | | | | | | The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. llvm-svn: 108099
* Replace copyRegToReg with copyPhysReg for CellSPU.Jakob Stoklund Olesen2010-07-112-34/+10
| | | | llvm-svn: 108084
* Switch SPU calling convention (function arguments) Kalle Raiskila2010-07-084-118/+52
| | | | | | to a Tablegen implementation. llvm-svn: 107913
* Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman2010-07-072-2/+6
| | | | | | code can do calling-convention queries. This obviates OutputArgReg. llvm-svn: 107786
* Propagate debug loc.Devang Patel2010-07-061-2/+3
| | | | llvm-svn: 107710
* Remove some unused/redundant code.Kalle Raiskila2010-07-052-20/+0
| | | | llvm-svn: 107622
* Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill ↵Evan Cheng2010-07-031-3/+2
| | | | | | slots so it's always false. llvm-svn: 107550
* Remove initialized but otherwise unused variables.Duncan Sands2010-06-291-1/+0
| | | | llvm-svn: 107127
* The hasMemory argument is irrelevant to how the argumentDale Johannesen2010-06-252-4/+1
| | | | | | | | | for an "i" constraint should get lowered; PR 6309. While this argument was passed around a lot, this is the only place it was used, so it goes away from a lot of other places. llvm-svn: 106893
* remove some dead variables reported by clang++Chris Lattner2010-06-211-2/+0
| | | | llvm-svn: 106428
* Mark the SPU 'lr' instruction to never have side effects. Kalle Raiskila2010-06-211-2/+0
| | | | | | | | | This allows the fast regiser allocator to remove redundant register moves. Update a set of tests that depend on the register allocator to be linear scan. llvm-svn: 106420
* Fix the lowering of VECTOR_SHUFFLE on SPU to handle splats.Kalle Raiskila2010-06-211-1/+1
| | | | llvm-svn: 106419
* Fix lowering of VECTOR_SHUFFLE on SPU. Old algorithmKalle Raiskila2010-06-211-9/+14
| | | | | | | used to choke llc with the attached test. llvm-svn: 106411
* Eliminate unnecessary uses of getZExtValue().Dan Gohman2010-06-181-1/+1
| | | | llvm-svn: 106279
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-172-9/+9
| | | | | | | | | | | | addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
* Fix SPU to cope with vector insertelement to an undef position.Kalle Raiskila2010-06-091-3/+8
| | | | | | We default to inserting to lane 0. llvm-svn: 105722
* Handle loading from/storing to undef pointers on SPU by inserting a Kalle Raiskila2010-06-091-1/+3
| | | | | | random load/store, rather than crashing llc. llvm-svn: 105710
* Flag SPU's function call sequence together. Kalle Raiskila2010-06-081-1/+1
| | | | | | | Discussed here: http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-June/032107.html llvm-svn: 105601
* cleanupRafael Espindola2010-06-022-34/+0
| | | | llvm-svn: 105322
* Fix handling of 'load' nodes.Kalle Raiskila2010-06-011-8/+2
| | | | llvm-svn: 105269
* Code refactoring: pull SchedPreference enum from TargetLowering.h to ↵Evan Cheng2010-05-191-1/+1
| | | | | | TargetMachine.h and put it in its own namespace. llvm-svn: 104147
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