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path: root/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp
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* Fix @llvm.frameaddress codegen. FP elimination optimization should be ↵Evan Cheng2008-09-261-1/+2
| | | | | | disabled when frame address is desired. Also add support for depth > 0. llvm-svn: 56683
* Trim unnecessary #includes.Dan Gohman2008-07-111-1/+0
| | | | llvm-svn: 53471
* Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminatingDan Gohman2008-07-011-3/+3
| | | | | | | | | | | | | | | | the need for a flavor operand, and add a new SDNode subclass, LabelSDNode, for use with them to eliminate the need for a label id operand. Change instruction selection to let these label nodes through unmodified instead of creating copies of them. Teach the MachineInstr emitter how to emit a MachineInstr directly from an ISD label node. This avoids the need for allocating SDNodes for the label id and flavor value, as well as SDNodes for each of the post-isel label, label id, and label flavor. llvm-svn: 52943
* Don't use ISD namespace opcodes for MachineInstrs.Dan Gohman2008-06-301-2/+2
| | | | llvm-svn: 52932
* Remove more iostream header includes. Needed to implement a "FlushStream"Bill Wendling2008-05-291-2/+1
| | | | | | function to flush a specified std::ostream. llvm-svn: 51705
* Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.Evan Cheng2008-03-311-9/+0
| | | | llvm-svn: 48995
* Fix newly-introduced 4.3 warningsAnton Korobeynikov2008-02-201-1/+1
| | | | llvm-svn: 47375
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-1/+1
| | | | llvm-svn: 46930
* Add an extra operand to LABEL nodes which distinguishes between debug, EH, ↵Evan Cheng2008-01-311-3/+3
| | | | | | or misc labels. This fixes the EH breakage. However I am not convinced this is *the* solution. llvm-svn: 46609
* More cleanups for CellSPU:Scott Michel2008-01-301-15/+15
| | | | | | | | | - Expand tabs... (poss 80-col violations, will get them later...) - Consolidate logic for SelectDFormAddr and SelectDForm2Addr into a single function, simplifying maintenance. Also reduced custom instruction generation for SPUvecinsert/INSERT_MASK. llvm-svn: 46544
* Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson2008-01-071-48/+0
| | | | | | Some day I'll get it all moved over... llvm-svn: 45672
* Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson2008-01-011-169/+0
| | | | llvm-svn: 45484
* Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson2007-12-311-37/+0
| | | | | | Machine-level API cleanup instigated by Chris. llvm-svn: 45470
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-4/+5
| | | | | | | | | | | | | | that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
* Add new shorter predicates for testing machine operands for various types: Chris Lattner2007-12-301-3/+3
| | | | | | | | | | | | e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner2007-12-301-9/+8
| | | | | | Likewise setImmedValue -> setImm llvm-svn: 45453
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-5/+4
| | | | llvm-svn: 45418
* More working CellSPU tests:Scott Michel2007-12-201-2/+4
| | | | | | | - vec_const.ll: Vector constant loads - immed64.ll: i64, f64 constant loads llvm-svn: 45242
* Add new immed16.ll test case, fix CellSPU errata to make test case work.Scott Michel2007-12-191-2/+0
| | | | llvm-svn: 45196
* - Restore some i8 functionality in CellSPUScott Michel2007-12-171-4/+5
| | | | | | - New test case: nand.ll llvm-svn: 45130
* Update foldMemoryOperand.Evan Cheng2007-12-051-2/+7
| | | | llvm-svn: 44621
* Add a argument to storeRegToStackSlot and storeRegToAddr to specify whetherEvan Cheng2007-12-051-3/+5
| | | | | | the stored register is killed. llvm-svn: 44600
* Updated source file headers to llvm coding standard.Scott Michel2007-12-051-3/+2
| | | | llvm-svn: 44597
* Main CellSPU backend files checked in. Intrinsics and autoconf filesScott Michel2007-12-051-0/+863
remain. llvm-svn: 44595
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