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path: root/llvm/lib/Target/CellSPU/SPUISelLowering.h
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* Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman2010-07-071-0/+2
| | | | | | code can do calling-convention queries. This obviates OutputArgReg. llvm-svn: 107786
* The hasMemory argument is irrelevant to how the argumentDale Johannesen2010-06-251-1/+0
| | | | | | | | | for an "i" constraint should get lowered; PR 6309. While this argument was passed around a lot, this is the only place it was used, so it goes away from a lot of other places. llvm-svn: 106893
* Use const qualifiers with TargetLowering. This eliminates severalDan Gohman2010-04-171-5/+5
| | | | | | | | | | | | | const_casts, and it reinforces the design of the Target classes being immutable. SelectionDAGISel::IsLegalToFold is now a static member function, because PIC16 uses it in an unconventional way. There is more room for API cleanup here. And PIC16's AsmPrinter no longer uses TargetLowering. llvm-svn: 101635
* Revert 95130.Evan Cheng2010-02-021-1/+1
| | | | llvm-svn: 95160
* Pass callsite return type to TargetLowering::LowerCall and use that to check ↵Evan Cheng2010-02-021-1/+1
| | | | | | sibcall eligibility. llvm-svn: 95130
* Eliminate target hook IsEligibleForTailCallOptimization.Evan Cheng2010-01-271-1/+1
| | | | | | | | | Target independent isel should always pass along the "tail call" property. Change target hook LowerCall's parameter "isTailCall" into a refernce. If the target decides it's impossible to honor the tail call request, it should set isTailCall to false to make target independent isel happy. llvm-svn: 94626
* Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.Sandeep Patel2009-09-021-3/+3
| | | | llvm-svn: 80773
* 128-bit sign extension and vector shift cleanups, contributed by Ken WernerScott Michel2009-08-241-3/+0
| | | | | | (IBM). llvm-svn: 79949
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-1/+1
| | | | | | | | while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-9/+9
| | | | | | own struct type. llvm-svn: 78610
* Start moving TargetLowering away from using full MVTs and towards ↵Owen Anderson2009-08-101-1/+1
| | | | | | SimpleValueType, which will simplify the privatization of IntegerType in the future. llvm-svn: 78584
* Major calling convention code refactoring.Dan Gohman2009-08-051-0/+22
| | | | | | | | | | | | | | | | | | | Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
* Small cleanups in the PowerPC backend.Tilmann Scheller2009-07-031-1/+0
| | | | | | | | | | Small refactoring in LowerFORMAL_ARGUMENTS(). Correct minor formatting issues. Remove size argument of CreateCopyOfByValArgument(). Remove dead argument from CalculateStackSlotSize(). Remove unused variable ReturnAddrIndex from various targets. llvm-svn: 74763
* Update comments to make it clear that the function alignment is the Log2 of theBill Wendling2009-07-011-1/+1
| | | | | | bytes and not bytes. llvm-svn: 74624
* Add an "alignment" field to the MachineFunction object. It makes more sense toBill Wendling2009-06-301-0/+3
| | | | | | | | | | have the alignment be calculated up front, and have the back-ends obey whatever alignment is decided upon. This allows for future work that would allow for precise no-op placement and the like. llvm-svn: 74564
* CellSPU:Scott Michel2009-03-171-4/+2
| | | | | | | | | | | | - Fix fabs, fneg for f32 and f64. - Use BuildVectorSDNode.isConstantSplat, now that the functionality exists - Continue to improve i64 constant lowering. Lower certain special constants to the constant pool when they correspond to SPU's shufb instruction's special mask values. This avoids the overhead of performing a shuffle on a zero-filled vector just to get the special constant when the memory load suffices. llvm-svn: 67067
* Get rid of one more non-DebugLoc getNode andDale Johannesen2009-02-061-3/+4
| | | | | | | its corresponding getTargetNode. Lots of caller changes. llvm-svn: 63904
* CellSPU:Scott Michel2009-01-261-2/+2
| | | | | | | | | | | | | | | | - Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll - Fix select_bits.ll test - Capitulate to the DAGCombiner and move i64 constant loads to instruction selection (SPUISelDAGtoDAG.cpp). <rant>DAGCombiner will insert all kinds of 64-bit optimizations after operation legalization occurs and now we have to do most of the work that instruction selection should be doing twice (once to determine if v2i64 build_vector can be handled by SelectCode(), which then runs all of the predicates a second time to select the necessary instructions.) But, CellSPU is a good citizen.</rant> llvm-svn: 62990
* CellSPU:Scott Michel2009-01-211-1/+2
| | | | | | | | | | | | | - Ensure that (operation) legalization emits proper FDIV libcall when needed. - Fix various bugs encountered during llvm-spu-gcc build, along with various cleanups. - Start supporting double precision comparisons for remaining libgcc2 build. Discovered interesting DAGCombiner feature, which is currently solved via custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner insists on inserting one anyway.) - Update README. llvm-svn: 62664
* - Convert remaining i64 custom lowering into custom instruction emissionScott Michel2009-01-151-4/+21
| | | | | | | | | | | | | sequences in SPUDAGToDAGISel.cpp and SPU64InstrInfo.td, killing custom DAG node types as needed. - i64 mul is now a legal instruction, but emits an instruction sequence that stretches tblgen and the imagination, as well as violating laws of several small countries and most southern US states (just kidding, but looking at a function with 80+ parameters is really weird and just plain wrong.) - Update tests as needed. llvm-svn: 62254
* CellSPU:Scott Michel2009-01-061-2/+0
| | | | | | | - Add preliminary support for v2i32; load/store generates the right code but there's a lot work to be done to make this vector type operational. llvm-svn: 61829
* Fix PR3274: when promoting the condition of a BRCOND node,Duncan Sands2009-01-011-1/+1
| | | | | | | | | | promote from i1 all the way up to the canonical SetCC type. In order to discover an appropriate type to use, pass MVT::Other to getSetCCResultType. In order to be able to do this, change getSetCCResultType to take a type as an argument, not a value (this is also more logical). llvm-svn: 61542
* - Start moving target-dependent nodes that could be represented by anScott Michel2008-12-301-16/+8
| | | | | | | | | | | | | instruction sequence and cannot ordinarily be simplified by DAGcombine into the various target description files or SPUDAGToDAGISel.cpp. This makes some 64-bit operations legal. - Eliminate target-dependent ISD enums. - Update tests. llvm-svn: 61508
* - Remove Tilmann's custom truncate lowering: it completely hosed overScott Michel2008-12-271-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | DAGcombine's ability to find reasons to remove truncates when they were not needed. Consequently, the CellSPU backend would produce correct, but _really slow and horrible_, code. Replaced with instruction sequences that do the equivalent truncation in SPUInstrInfo.td. - Re-examine how unaligned loads and stores work. Generated unaligned load code has been tested on the CellSPU hardware; see the i32operations.c and i64operations.c in CodeGen/CellSPU/useful-harnesses. (While they may be toy test code, it does prove that some real world code does compile correctly.) - Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc fault because i64 ult is not yet implemented.) - Added i64 eq and neq for setcc and select/setcc; started new instruction information file for them in SPU64InstrInfo.td. Additional i64 operations should be added to this file and not to SPUInstrInfo.td. llvm-svn: 61447
* CellSPU:Scott Michel2008-12-041-6/+0
| | | | | | | | | | | | | | | | | | | | | | - First patch from Nehal Desai, a new contributor at Aerospace. Nehal's patch fixes sign/zero/any-extending loads for integers and floating point. Example code, compiled w/o debugging or optimization where he first noticed the bug: int main(void) { float a = 99.0; printf("%d\n", a); return 0; } Verified that this code actually works on a Cell SPU. Changes by Scott Michel: - Fix bug in the value type list constructed by SPUISD::LDRESULT to include both the load result's result and chain, not just the chain alone. - Simplify LowerLOAD and remove extraneous and unnecessary chains. - Remove unused SPUISD pseudo instructions. llvm-svn: 60526
* Change the interface to the type legalization methodDuncan Sands2008-12-011-3/+4
| | | | | | | | | | | ReplaceNodeResults: rather than returning a node which must have the same number of results as the original node (which means mucking around with MERGE_VALUES, and which is also easy to get wrong since SelectionDAG folding may mean you don't get the node you expect), return the results in a vector. llvm-svn: 60348
* CellSPU:Scott Michel2008-11-241-3/+2
| | | | | | | | | | (a) Improve the extract element code: there's no need to do gymnastics with rotates into the preferred slot if a shuffle will do the same thing. (b) Rename a couple of SPUISD pseudo-instructions for readability and better semantic correspondence. (c) Fix i64 sign/any/zero extension lowering. llvm-svn: 59965
* CellSPU: Fix bug 3056. Varadic extract_element was not implemented (nor was itScott Michel2008-11-221-1/+1
| | | | | | ever conceived to occur). llvm-svn: 59891
* CellSPU: Fix bug 3606, as well as some ongoing work.Scott Michel2008-11-101-2/+4
| | | | llvm-svn: 59009
* Teach DAGCombine to fold constant offsets into GlobalAddress nodes,Dan Gohman2008-10-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | and add a TargetLowering hook for it to use to determine when this is legal (i.e. not in PIC mode, etc.) This allows instruction selection to emit folded constant offsets in more cases, such as the included testcase, eliminating the need for explicit arithmetic instructions. This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp that attempted to achieve the same effect, but wasn't as effective. Also, fix handling of offsets in GlobalAddressSDNodes in several places, including changing GlobalAddressSDNode's offset from int to int64_t. The Mips, Alpha, Sparc, and CellSPU targets appear to be unaware of GlobalAddress offsets currently, so set the hook to false on those targets. llvm-svn: 57748
* Properly handle 'm' inline asm constraints. If a GV is being selected for ↵Evan Cheng2008-09-241-0/+1
| | | | | | the addressing mode, it requires the same logic for PIC relative addressing, etc. llvm-svn: 56526
* Fix these enums' starting values to reflect the way thatDan Gohman2008-09-231-1/+1
| | | | | | instruction opcodes are now numbered. No functionality change. llvm-svn: 56497
* Rename SDOperand to SDValue.Dan Gohman2008-07-271-13/+13
| | | | llvm-svn: 54128
* Wrap MVT::ValueType in a struct to get type safetyDuncan Sands2008-06-061-7/+7
| | | | | | | | | | | | | | | | and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
* Add necessary 64-bit support so that gcc frontend compiles (mostly). CurrentScott Michel2008-06-021-1/+6
| | | | | | | issue is operand promotion for setcc/select... but looks like the fundamental stuff is implemented for CellSPU. llvm-svn: 51884
* Bug fixes and updates for CellSPU, syncing up with trunk. Most notableScott Michel2008-04-301-0/+4
| | | | | | | | fixes are target-specific lowering of frame indices, fix constants generated for the FSMBI instruction, and fixing SPUTargetLowering::computeMaskedBitsFor- TargetNode(). llvm-svn: 50462
* no need to implement this method and just have it callChris Lattner2008-04-261-4/+0
| | | | | | the default impl. llvm-svn: 50311
* Integer comparison tests for CellSPU.Scott Michel2008-03-101-1/+1
| | | | llvm-svn: 48152
* Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC'sScott Michel2008-03-101-0/+3
| | | | | | | | return ValueType can depend its operands' ValueType. This is a cosmetic change, no functionality impacted. llvm-svn: 48145
* Merge current work back to tree to minimize diffs and drift. Major highlightsScott Michel2008-02-231-1/+4
| | | | | | | | | | | | | | for CellSPU modifications: - SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend. - Other improvements based on refactoring effort in SPUISelLowering.cpp, esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and rotates are now eliminiated, other scalar-to-vector-to-scalar silliness is also eliminated. - 64-bit operations are being implemented, _muldi3.c gcc runtime now compiles and generates the right code. More work still needs to be done. llvm-svn: 47532
* Fix single precision FP constants on SPU. They are actually legal,Nate Begeman2008-02-141-1/+0
| | | | | | which allows us to kill a target-specific node. llvm-svn: 47127
* Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBitsDan Gohman2008-02-131-1/+1
| | | | | | to pass the mask APInt by value, not by reference. llvm-svn: 47096
* Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.Dan Gohman2008-02-131-3/+3
| | | | | | | Add an overload that supports the uint64_t interface for use by clients that haven't been updated yet. llvm-svn: 47039
* Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a ↵Evan Cheng2008-01-301-3/+0
| | | | | | | | proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert instruction at the end. llvm-svn: 46562
* More cleanups for CellSPU:Scott Michel2008-01-301-20/+20
| | | | | | | | | - Expand tabs... (poss 80-col violations, will get them later...) - Consolidate logic for SelectDFormAddr and SelectDForm2Addr into a single function, simplifying maintenance. Also reduced custom instruction generation for SPUvecinsert/INSERT_MASK. llvm-svn: 46544
* Overhaul Cell SPU's addressing mode internals so that there are nowScott Michel2008-01-291-2/+1
| | | | | | | | | | | | | | only two addressing mode nodes, SPUaform and SPUindirect (vice the three previous ones, SPUaform, SPUdform and SPUxform). This improves code somewhat because we now avoid using reg+reg addressing when it can be avoided. It also simplifies the address selection logic, which was the main point for doing this. Also, for various global variables that would be loaded using SPU's A-form addressing, prefer D-form offs[reg] addressing, keeping the base in a register if the variable is used more than once. llvm-svn: 46483
* More CellSPU refinement and progress:Scott Michel2008-01-111-1/+2
| | | | | | | | | | | | | | | | | | | | - Cleaned up custom load/store logic, common code is now shared [see note below], cleaned up address modes - More test cases: various intrinsics, structure element access (load/store test), updated target data strings, indirect function calls. Note: This patch contains a refactoring of the LoadSDNode and StoreSDNode structures: they now share a common base class, LSBaseSDNode, that provides an interface to their common functionality. There is some hackery to access the proper operand depending on the derived class; otherwise, to do a proper job would require finding and rearranging the SDOperands sent to StoreSDNode's constructor. The current refactor errs on the side of being conservatively and backwardly compatible while providing functionality that reduces redundant code for targets where loads and stores are custom-lowered. llvm-svn: 45851
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-3/+2
| | | | llvm-svn: 45418
* Updated source file headers to llvm coding standard.Scott Michel2007-12-051-3/+2
| | | | llvm-svn: 44597
* More of the Cell SPU code drop from "Team Aerospace".Scott Michel2007-12-041-0/+139
llvm-svn: 44582
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