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| author | Scott Michel <scottm@aero.org> | 2008-06-02 22:18:03 +0000 |
|---|---|---|
| committer | Scott Michel <scottm@aero.org> | 2008-06-02 22:18:03 +0000 |
| commit | d831cc49e5c9d4623b1370a268f078ff06b4586a (patch) | |
| tree | d86f3a350404314bd8283ef7ecae8797df0ae14f /llvm/lib/Target/CellSPU/SPUISelLowering.h | |
| parent | 88bfb62ffe96526e7aaba609ca015f47490b47f4 (diff) | |
| download | bcm5719-llvm-d831cc49e5c9d4623b1370a268f078ff06b4586a.tar.gz bcm5719-llvm-d831cc49e5c9d4623b1370a268f078ff06b4586a.zip | |
Add necessary 64-bit support so that gcc frontend compiles (mostly). Current
issue is operand promotion for setcc/select... but looks like the fundamental
stuff is implemented for CellSPU.
llvm-svn: 51884
Diffstat (limited to 'llvm/lib/Target/CellSPU/SPUISelLowering.h')
| -rw-r--r-- | llvm/lib/Target/CellSPU/SPUISelLowering.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.h b/llvm/lib/Target/CellSPU/SPUISelLowering.h index 3c73aa51c06..5632ee3152c 100644 --- a/llvm/lib/Target/CellSPU/SPUISelLowering.h +++ b/llvm/lib/Target/CellSPU/SPUISelLowering.h @@ -62,8 +62,13 @@ namespace llvm { ROTBYTES_RIGHT_S, ///< Vector rotate right, by bytes, sign fill ROTBYTES_LEFT, ///< Rotate bytes (loads -> ROTQBYI) ROTBYTES_LEFT_CHAINED, ///< Rotate bytes (loads -> ROTQBYI), with chain - FSMBI, ///< Form Select Mask for Bytes, Immediate + ROTBYTES_LEFT_BITS, ///< Rotate bytes left by bit shift count + SELECT_MASK, ///< Select Mask (FSM, FSMB, FSMH, FSMBI) SELB, ///< Select bits -> (b & mask) | (a & ~mask) + ADD_EXTENDED, ///< Add extended, with carry + CARRY_GENERATE, ///< Carry generate for ADD_EXTENDED + SUB_EXTENDED, ///< Subtract extended, with borrow + BORROW_GENERATE, ///< Borrow generate for SUB_EXTENDED FPInterp, ///< Floating point interpolate FPRecipEst, ///< Floating point reciprocal estimate SEXT32TO64, ///< Sign-extended 32-bit const -> 64-bits |
