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path: root/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
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* Use i8 as SETCC result type for i1 in SPU.Kalle Raiskila2010-11-241-4/+14
| | | | llvm-svn: 120092
* Division by pow-of-2 is not cheap on SPU, do it with Kalle Raiskila2010-11-231-2/+0
| | | | | | shifts. llvm-svn: 120022
* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-231-92/+92
| | | | llvm-svn: 119990
* Fix a bug with extractelement on SPU.Kalle Raiskila2010-11-221-1/+1
| | | | | | | In the attached testcase, the element was never extracted (missing rotate). llvm-svn: 119973
* Improve code layout, mostly indentation. Kalle Raiskila2010-11-151-166/+150
| | | | | | No functionality change. llvm-svn: 119142
* Fix memory access lowering on SPU, addingKalle Raiskila2010-11-121-102/+219
| | | | | | | | | | | | support for the case where alignment<value size. These cases were silently miscompiled before this patch. Now they are overly verbose -especially storing is- and any front-end should still avoid misaligned memory accesses as much as possible. The bit juggling algorithm added here probably has some room for improvement still. llvm-svn: 118889
* Simplify uses of MVT and EVT. An MVT can be compared directlyDuncan Sands2010-11-031-1/+1
| | | | | | | with a SimpleValueType, while an EVT supports equality and inequality comparisons with SimpleValueType. llvm-svn: 118169
* Inline asm multiple alternative constraints development phase 2 - improved ↵John Thompson2010-10-291-0/+33
| | | | | | basic logic, added initial platform support. llvm-svn: 117667
* Improve lowering of sext to i128 on SPU.Kalle Raiskila2010-10-181-2/+7
| | | | | | | | The old algorithm inserted a 'rotqmbyi' instruction which was both redundant and wrong - it made shufb select bytes from the wrong end of the input quad. llvm-svn: 116701
* Implement two virtual functions in SPUTargetLowering.Kalle Raiskila2010-10-071-0/+26
| | | | | | | | | | Before the implementation of isLegalAddressingMode, some rare cases of code were miscompiled if optimized with the LoopStrengthReduce pass. It is unclear (to me) if LSR is "allowed" to produce wrong code with a bad TargetLowering, or if the bug is elsewhere and this patch just hides it. llvm-svn: 115919
* update a bunch of code to use the MachinePointerInfo version of getStore.Chris Lattner2010-09-211-3/+4
| | | | llvm-svn: 114461
* it's more elegant to put the "getConstantPool" andChris Lattner2010-09-211-3/+4
| | | | | | | | "getFixedStack" on the MachinePointerInfo class. While this isn't the problem I'm setting out to solve, it is the right way to eliminate PseudoSourceValue, so lets go with it. llvm-svn: 114406
* Silence compiler warning.Kalle Raiskila2010-09-091-1/+1
| | | | llvm-svn: 113478
* Fix CellSPU vector shuffles, again.Kalle Raiskila2010-09-081-7/+7
| | | | | | Some cases of lowering to rotate were miscompiled. llvm-svn: 113355
* Fix lowering of INSERT_VECTOR_ELT in SPU. Kalle Raiskila2010-08-291-3/+4
| | | | | | The IDX was treated as byte index, not element index. llvm-svn: 112422
* Fix SPU BE to use all the available return registers.Kalle Raiskila2010-08-241-34/+16
| | | | | | llc used to assert on the added testcase. llvm-svn: 111911
* Remove some dead code from SPU BE that remainedKalle Raiskila2010-08-241-18/+6
| | | | | | from 64bit vector support. llvm-svn: 111910
* Fix a bug with insertelement on SPU. Kalle Raiskila2010-08-181-6/+11
| | | | | | | The previous algorithm in LowerVECTOR_SHUFFLE didn't check all requirements for "monotonic" shuffles. llvm-svn: 111361
* Remove all traces of v2[i,f]32 on SPU. Kalle Raiskila2010-08-181-27/+0
| | | | | | | | The "half vectors" are now widened to full size by the legalizer. The only exception is in parameter passing, where half vectors are expanded. This causes changes to some dejagnu tests. llvm-svn: 111360
* Have SPU handle halfvec stores aligned by 8 bytes.Kalle Raiskila2010-08-091-9/+26
| | | | llvm-svn: 110576
* Make SPU backend handle insertelement and Kalle Raiskila2010-08-041-1/+4
| | | | | | store for "half vectors" llvm-svn: 110198
* More SPU v2f32 stuff added: insertelement and shuffle.Kalle Raiskila2010-08-021-0/+1
| | | | llvm-svn: 110038
* Add preliminary v2f32 support for SPU. Like with v2i32, we justKalle Raiskila2010-08-021-0/+2
| | | | | | | | duplicate the instructions and operate on half vectors. Also reorder code in SPUInstrInfo.td for better coherency. llvm-svn: 110037
* Add preliminary v2i32 support for SPU backend. As there are noKalle Raiskila2010-08-021-3/+16
| | | | | | | | | | such registers in SPU, this support boils down to "emulating" them by duplicating instructions on the general purpose registers. This adds the most basic operations on v2i32: passing parameters, addition, subtraction, multiplication and a few others. llvm-svn: 110035
* Switch SPU calling convention (function arguments) Kalle Raiskila2010-07-081-12/+40
| | | | | | to a Tablegen implementation. llvm-svn: 107913
* Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman2010-07-071-2/+4
| | | | | | code can do calling-convention queries. This obviates OutputArgReg. llvm-svn: 107786
* Propagate debug loc.Devang Patel2010-07-061-2/+3
| | | | llvm-svn: 107710
* Remove some unused/redundant code.Kalle Raiskila2010-07-051-16/+0
| | | | llvm-svn: 107622
* Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill ↵Evan Cheng2010-07-031-3/+2
| | | | | | slots so it's always false. llvm-svn: 107550
* The hasMemory argument is irrelevant to how the argumentDale Johannesen2010-06-251-3/+1
| | | | | | | | | for an "i" constraint should get lowered; PR 6309. While this argument was passed around a lot, this is the only place it was used, so it goes away from a lot of other places. llvm-svn: 106893
* remove some dead variables reported by clang++Chris Lattner2010-06-211-2/+0
| | | | llvm-svn: 106428
* Fix the lowering of VECTOR_SHUFFLE on SPU to handle splats.Kalle Raiskila2010-06-211-1/+1
| | | | llvm-svn: 106419
* Fix lowering of VECTOR_SHUFFLE on SPU. Old algorithmKalle Raiskila2010-06-211-9/+14
| | | | | | | used to choke llc with the attached test. llvm-svn: 106411
* Eliminate unnecessary uses of getZExtValue().Dan Gohman2010-06-181-1/+1
| | | | llvm-svn: 106279
* Fix SPU to cope with vector insertelement to an undef position.Kalle Raiskila2010-06-091-3/+8
| | | | | | We default to inserting to lane 0. llvm-svn: 105722
* Code refactoring: pull SchedPreference enum from TargetLowering.h to ↵Evan Cheng2010-05-191-1/+1
| | | | | | TargetMachine.h and put it in its own namespace. llvm-svn: 104147
* teach cellspu how to return i8 and i16 from calls,Chris Lattner2010-04-201-12/+2
| | | | | | patch by Kalle Raiskila! llvm-svn: 101875
* Use const qualifiers with TargetLowering. This eliminates severalDan Gohman2010-04-171-8/+9
| | | | | | | | | | | | | const_casts, and it reinforces the design of the Target classes being immutable. SelectionDAGISel::IsLegalToFold is now a static member function, because PIC16 uses it in an unconventional way. There is more room for API cleanup here. And PIC16's AsmPrinter no longer uses TargetLowering. llvm-svn: 101635
* Move per-function state out of TargetLowering subclasses and intoDan Gohman2010-04-171-3/+6
| | | | | | MachineFunctionInfo subclasses. llvm-svn: 101634
* Add const qualifiers to CodeGen's use of LLVM IR constructs.Dan Gohman2010-04-151-3/+3
| | | | llvm-svn: 101334
* Use twines to simplify calls to report_fatal_error. For code size and ↵Benjamin Kramer2010-04-081-31/+14
| | | | | | readability. llvm-svn: 100756
* rename llvm::llvm_report_error -> llvm::report_fatal_errorChris Lattner2010-04-071-9/+9
| | | | llvm-svn: 100709
* Remove a bunch of integer width predicate functions in favor of MathExtras.Benjamin Kramer2010-03-291-1/+1
| | | | | | | Most of these were unused, some of them were wrong and unused (isS16Constant<short>, isS10Constant<short>). llvm-svn: 99827
* From Kalle Raiskila:Chris Lattner2010-03-291-1/+2
| | | | | | | | "the bigstack patch for SPU, with testcase. It is essentially the patch committed as 97091, and reverted as 97099, but with the following additions: -in vararg handling, registers are marked to be live, to not confuse the register scavenger -function prologue and epilogue are not emitted, if the stack size is 16. 16 means it is empty - there is only the register scavenger emergency spill slot, which is not used as there is no stack." llvm-svn: 99819
* Remove dead parameter passing.Bill Wendling2010-03-021-2/+1
| | | | llvm-svn: 97536
* Move TLOF implementations to libCodegen to resolve layering violation.Anton Korobeynikov2010-02-151-1/+1
| | | | llvm-svn: 96288
* Remove an assumption of default arguments. This is in anticipation of aDavid Greene2010-02-151-8/+13
| | | | | | change to SelectionDAG build APIs. llvm-svn: 96232
* Revert 95130.Evan Cheng2010-02-021-1/+1
| | | | llvm-svn: 95160
* Pass callsite return type to TargetLowering::LowerCall and use that to check ↵Evan Cheng2010-02-021-1/+1
| | | | | | sibcall eligibility. llvm-svn: 95130
* Eliminate target hook IsEligibleForTailCallOptimization.Evan Cheng2010-01-271-1/+3
| | | | | | | | | Target independent isel should always pass along the "tail call" property. Change target hook LowerCall's parameter "isTailCall" into a refernce. If the target decides it's impossible to honor the tail call request, it should set isTailCall to false to make target independent isel happy. llvm-svn: 94626
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