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path: root/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
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* Use CHAR_BIT instead of hard-coding 8 in several places where itDan Gohman2009-04-011-1/+1
| | | | | | | is appropriate. This helps visually differentiate host-oriented calculations from target-oriented calculations. llvm-svn: 68227
* fix warning in -asserts mode.Chris Lattner2009-03-261-4/+3
| | | | llvm-svn: 67739
* CellSPU:Scott Michel2009-03-171-260/+118
| | | | | | | | | | | | - Fix fabs, fneg for f32 and f64. - Use BuildVectorSDNode.isConstantSplat, now that the functionality exists - Continue to improve i64 constant lowering. Lower certain special constants to the constant pool when they correspond to SPU's shufb instruction's special mask values. This avoids the overhead of performing a shuffle on a zero-filled vector just to get the special constant when the memory load suffices. llvm-svn: 67067
* CellSPU:Scott Michel2009-03-161-19/+15
| | | | | | | Incorporate Tilmann's 128-bit operation patch. Evidently, it gets the llvm-gcc bootstrap a bit further along. llvm-svn: 67048
* Revert BuildVectorSDNode related patches: 65426, 65427, and 65296.Evan Cheng2009-02-251-42/+44
| | | | llvm-svn: 65482
* Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTORScott Michel2009-02-221-44/+42
| | | | | | | | | instruction. The class also consolidates the code for detecting constant splats that's shared across PowerPC and the CellSPU backends (and might be useful for other backends.) Also introduces SelectionDAG::getBUID_VECTOR() for generating new BUILD_VECTOR nodes. llvm-svn: 65296
* Use getDebugLoc forwarder instead of getNode()->getDebugLoc.Dale Johannesen2009-02-071-2/+2
| | | | | | No functional change. llvm-svn: 64026
* Get rid of the last non-DebugLoc versions of getNode!Dale Johannesen2009-02-071-3/+3
| | | | | | | | | | | | Many targets build placeholder nodes for special operands, e.g. GlobalBaseReg on X86 and PPC for the PIC base. There's no sensible way to associate debug info with these. I've left them built with getNode calls with explicit DebugLoc::getUnknownLoc operands. I'm not too happy about this but don't see a good improvement; I considered adding a getPseudoOperand or something, but it seems to me that'll just make it harder to read. llvm-svn: 63992
* Remove more non-DebugLoc versions of getNode.Dale Johannesen2009-02-061-37/+49
| | | | llvm-svn: 63969
* Get rid of one more non-DebugLoc getNode andDale Johannesen2009-02-061-73/+82
| | | | | | | its corresponding getTargetNode. Lots of caller changes. llvm-svn: 63904
* Remove non-DebugLoc forms of CopyToReg and CopyFromReg.Dale Johannesen2009-02-041-35/+41
| | | | | | Adjust callers. llvm-svn: 63789
* Remove non-DebugLoc versions of getLoad and getStore.Dale Johannesen2009-02-041-42/+52
| | | | | | Adjust the many callers of those versions. llvm-svn: 63767
* Remove some more non-DebugLoc versions of constructionDale Johannesen2009-02-041-23/+25
| | | | | | functions, with callers adjusted to fit. llvm-svn: 63705
* Make LowerCallTo and LowerArguments take a DebugLocDale Johannesen2009-01-301-1/+2
| | | | | | argument. Adjust all callers and overloaded versions. llvm-svn: 63444
* CellSPU:Scott Michel2009-01-261-3/+4
| | | | | | - Update DWARF debugging support. llvm-svn: 63059
* Untabify code.Scott Michel2009-01-261-5/+5
| | | | llvm-svn: 62991
* CellSPU:Scott Michel2009-01-261-186/+298
| | | | | | | | | | | | | | | | - Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll - Fix select_bits.ll test - Capitulate to the DAGCombiner and move i64 constant loads to instruction selection (SPUISelDAGtoDAG.cpp). <rant>DAGCombiner will insert all kinds of 64-bit optimizations after operation legalization occurs and now we have to do most of the work that instruction selection should be doing twice (once to determine if v2i64 build_vector can be handled by SelectCode(), which then runs all of the predicates a second time to select the necessary instructions.) But, CellSPU is a good citizen.</rant> llvm-svn: 62990
* CellSPU:Scott Michel2009-01-211-54/+126
| | | | | | | | | | | | | - Ensure that (operation) legalization emits proper FDIV libcall when needed. - Fix various bugs encountered during llvm-spu-gcc build, along with various cleanups. - Start supporting double precision comparisons for remaining libgcc2 build. Discovered interesting DAGCombiner feature, which is currently solved via custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner insists on inserting one anyway.) - Update README. llvm-svn: 62664
* - Convert remaining i64 custom lowering into custom instruction emissionScott Michel2009-01-151-133/+39
| | | | | | | | | | | | | sequences in SPUDAGToDAGISel.cpp and SPU64InstrInfo.td, killing custom DAG node types as needed. - i64 mul is now a legal instruction, but emits an instruction sequence that stretches tblgen and the imagination, as well as violating laws of several small countries and most southern US states (just kidding, but looking at a function with 80+ parameters is really weird and just plain wrong.) - Update tests as needed. llvm-svn: 62254
* CellSPU:Scott Michel2009-01-061-33/+9
| | | | | | | - Add preliminary support for v2i32; load/store generates the right code but there's a lot work to be done to make this vector type operational. llvm-svn: 61829
* CellSPU:Scott Michel2009-01-061-15/+49
| | | | | | | | | | | | - Fix bugs 3194, 3195: i128 load/stores produce correct code (although, we need to ensure that i128 is 16-byte aligned in real life), and 128 zero- extends are supported. - New td file: SPU128InstrInfo.td: this is where all new i128 support should be put in the future. - Continue to hammer on i64 operations and test cases; ensure that the only remaining problem will be i64 mul. llvm-svn: 61784
* CellSPU:Scott Michel2009-01-031-35/+1
| | | | | | | | | - Remove custom lowering for BRCOND - Add remaining functionality for branches in SPUInstrInfo, such as branch condition reversal and load/store folding. Updated BrCond test to reflect branch reversal. llvm-svn: 61597
* Fix PR3274: when promoting the condition of a BRCOND node,Duncan Sands2009-01-011-3/+3
| | | | | | | | | | promote from i1 all the way up to the canonical SetCC type. In order to discover an appropriate type to use, pass MVT::Other to getSetCCResultType. In order to be able to do this, change getSetCCResultType to take a type as an argument, not a value (this is also more logical). llvm-svn: 61542
* - Start moving target-dependent nodes that could be represented by anScott Michel2008-12-301-351/+36
| | | | | | | | | | | | | instruction sequence and cannot ordinarily be simplified by DAGcombine into the various target description files or SPUDAGToDAGISel.cpp. This makes some 64-bit operations legal. - Eliminate target-dependent ISD enums. - Update tests. llvm-svn: 61508
* - Various '#if 0' cleanups.Scott Michel2008-12-291-61/+40
| | | | | | | | | - Move v4i32, i32 mul into SPUInstrInfo.td, with a few more instruction cleanups there as well. - Make SMUL_LOHI, UMUL_LOHI competely illegal for Cell SPU, to better assist Chris to see the problem in bug 3101. llvm-svn: 61464
* - Remove Tilmann's custom truncate lowering: it completely hosed overScott Michel2008-12-271-387/+410
| | | | | | | | | | | | | | | | | | | | | | | | DAGcombine's ability to find reasons to remove truncates when they were not needed. Consequently, the CellSPU backend would produce correct, but _really slow and horrible_, code. Replaced with instruction sequences that do the equivalent truncation in SPUInstrInfo.td. - Re-examine how unaligned loads and stores work. Generated unaligned load code has been tested on the CellSPU hardware; see the i32operations.c and i64operations.c in CodeGen/CellSPU/useful-harnesses. (While they may be toy test code, it does prove that some real world code does compile correctly.) - Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc fault because i64 ult is not yet implemented.) - Added i64 eq and neq for setcc and select/setcc; started new instruction information file for them in SPU64InstrInfo.td. Additional i64 operations should be added to this file and not to SPUInstrInfo.td. llvm-svn: 61447
* CellSPU:Scott Michel2008-12-101-8/+6
| | | | | | | | | - Fix bug 3185, with misc other cleanups. - Needed to implement SPUInstrInfo::InsertBranch(). CAUTION: Not sure what gets or needs to get passed to InsertBranch() to insert a conditional branch. This will abort for now until a good test case shows up. llvm-svn: 60811
* CellSPU:Scott Michel2008-12-091-2/+5
| | | | | | | | - Change default scheduling preference to list-burr, which produces somewhat better code than the default. Could also use list-tdrr, but need to ask dev list about the appropriate handy mnemonic before commiting. llvm-svn: 60738
* CellSPU: Fix bug 3055Scott Michel2008-12-041-22/+55
| | | | | | | | | - Add v4f32, v2f64 to LowerVECTOR_SHUFFLE - Look for vector rotate in shuffle elements, generate a vector rotate instead of a full-blown shuffle when opportunity presents itself. - Generate larger test harness and fix a few interesting but obscure bugs. llvm-svn: 60552
* Missing closing brace and reverse conditional condition on NDEBUGScott Michel2008-12-041-5/+5
| | | | llvm-svn: 60541
* This code is apparently quite confused. In the meantime,Chris Lattner2008-12-041-1/+2
| | | | | | get it building when NDEBUG is set. llvm-svn: 60532
* CellSPU:Scott Michel2008-12-041-65/+55
| | | | | | | | | | | | | | | | | | | | | | - First patch from Nehal Desai, a new contributor at Aerospace. Nehal's patch fixes sign/zero/any-extending loads for integers and floating point. Example code, compiled w/o debugging or optimization where he first noticed the bug: int main(void) { float a = 99.0; printf("%d\n", a); return 0; } Verified that this code actually works on a Cell SPU. Changes by Scott Michel: - Fix bug in the value type list constructed by SPUISD::LDRESULT to include both the load result's result and chain, not just the chain alone. - Simplify LowerLOAD and remove extraneous and unnecessary chains. - Remove unused SPUISD pseudo instructions. llvm-svn: 60526
* CellSPU:Scott Michel2008-12-021-1/+109
| | | | | | | | | | - Incorporate Tilmann Scheller's ISD::TRUNCATE custom lowering patch - Update SPU calling convention info, even if it's not used yet (but can be at some point or another) - Ensure that any-extended f32 loads are custom lowered, especially when they're promoted for use in printf. llvm-svn: 60438
* CellSPU:Scott Michel2008-12-011-37/+39
| | | | | | | | | - Fix v2[if]64 vector insertion code before IBM files a bug report. - Ensure that zero (0) offsets relative to $sp don't trip an assert (add $sp, 0 gets legalized to $sp alone, tripping an assert) - Shuffle masks passed to SPUISD::SHUFB are now v16i8 or v4i32 llvm-svn: 60358
* There are no longer any places that require aDuncan Sands2008-12-011-2/+2
| | | | | | | | MERGE_VALUES node with only one operand, so get rid of special code that only existed to handle that possibility. llvm-svn: 60349
* Change the interface to the type legalization methodDuncan Sands2008-12-011-2/+3
| | | | | | | | | | | ReplaceNodeResults: rather than returning a node which must have the same number of results as the original node (which means mucking around with MERGE_VALUES, and which is also easy to get wrong since SelectionDAG folding may mean you don't get the node you expect), return the results in a vector. llvm-svn: 60348
* CellSPU: Fix mnemonic typo in pattern; "shlqbyi" -> "shlqby".Scott Michel2008-11-251-0/+2
| | | | llvm-svn: 59998
* CellSPU:Scott Michel2008-11-241-4/+15
| | | | | | | | | (a) Slight rethink on i64 zero/sign/any extend code - use a shuffle to directly zero-extend i32 to i64, but use rotates and shifts for sign extension. Also ensure unified register consistency. (b) Add new test harness for i64 operations: i64ops.ll llvm-svn: 59970
* CellSPU:Scott Michel2008-11-241-87/+59
| | | | | | | | | | (a) Improve the extract element code: there's no need to do gymnastics with rotates into the preferred slot if a shuffle will do the same thing. (b) Rename a couple of SPUISD pseudo-instructions for readability and better semantic correspondence. (c) Fix i64 sign/any/zero extension lowering. llvm-svn: 59965
* Rename SetCCResultContents to BooleanContents. InDuncan Sands2008-11-231-1/+1
| | | | | | | practice these booleans are mostly produced by SetCC, however the concept is more general. llvm-svn: 59911
* CellSPU: Fix bug 3056. Varadic extract_element was not implemented (nor was itScott Michel2008-11-221-78/+242
| | | | | | ever conceived to occur). llvm-svn: 59891
* CellSPU:Scott Michel2008-11-211-32/+34
| | | | | | | | (a) Fix bgs 3052, 3057 (b) Incorporate Duncan's suggestions re: i1 promotion (c) Indentation updates. llvm-svn: 59790
* CellSPU:Scott Michel2008-11-201-6/+5
| | | | | | | | (a) Remove moved file (SPUAsmPrinter.cpp) to make svn happy. (b) Remove truncated stores that will never be used. (c) Add initial support for __muldi3 as a libcall. llvm-svn: 59734
* CellSPU: Custom lower truncating stores of i8 to i1 (should not have beenScott Michel2008-11-201-1/+1
| | | | | | promote), fix signed conversion of indexed offsets. llvm-svn: 59707
* CellSPU: Adjust spacing/tabulationScott Michel2008-11-201-8/+8
| | | | llvm-svn: 59703
* CellSPU: Do not custom lower i1 stores, rely on type legalization to do theScott Michel2008-11-191-34/+11
| | | | | | right thing and promote the store to i8. llvm-svn: 59648
* Temporary check-in for Duncan to demonstrate CellSPU store problem.Scott Michel2008-11-191-8/+41
| | | | llvm-svn: 59637
* Unbreak the buildbot and back out (inadvertant) casting edits in CellSPUScott Michel2008-11-111-7/+7
| | | | | | backend. llvm-svn: 59018
* CellSPU: Fix bug 3606, as well as some ongoing work.Scott Michel2008-11-101-10/+33
| | | | llvm-svn: 59009
* Use getTargetConstant instead of getConstant for nodes that should not be ↵Dan Gohman2008-11-051-8/+8
| | | | | | | | visited by isel and potentially forced into registers. llvm-svn: 58747
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