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* Fixed Overload table bug noticed by JakobMon P Wang2009-11-071-1/+0
| | | | llvm-svn: 86332
* Reintroduce support for overloading target intrinsicsMon P Wang2009-11-052-3/+55
| | | | llvm-svn: 86114
* Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this ↵Anton Korobeynikov2009-11-021-5/+5
| | | | | | | won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364. PS: It seems that blackfin usage of copy_to_regclass is completely bogus! llvm-svn: 85766
* Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.Nick Lewycky2009-10-251-1/+1
| | | | | | | Chris claims we should never have visibility_hidden inside any .cpp file but that's still not true even after this commit. llvm-svn: 85042
* Move Blackfin intrinsics into the Target/Blackfin directory.Jakob Stoklund Olesen2009-10-157-1/+124
| | | | llvm-svn: 84194
* Add register-reuse to frame-index register scavenging. When a target usesJim Grosbach2009-10-072-8/+11
| | | | | | | | | | | | | | | | | | | | a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. llvm-svn: 83467
* Instead of printing unnecessary basic block labels as labels inDan Gohman2009-10-061-7/+1
| | | | | | | | | | verbose-asm mode, print comments instead. This eliminates a non-comment difference between verbose-asm mode and non-verbose-asm mode. Also, factor out the relevant code out of all the targets and into target-independent code. llvm-svn: 83392
* Update processDebugLoc() so that it can be used to process debug info before ↵Devang Patel2009-10-061-1/+2
| | | | | | and after printing an instruction. llvm-svn: 83363
* Use MachineInstr as an processDebugLoc() argument.Devang Patel2009-09-301-1/+1
| | | | | | This will allow processDebugLoc() to handle scopes for DWARF debug info. llvm-svn: 83183
* Rename getTargetNode to getMachineNode, for consistency with theDan Gohman2009-09-252-17/+17
| | | | | | | | naming scheme used in SelectionDAG, where there are multiple kinds of "target" nodes, but "machine" nodes are nodes which represent a MachineInstr. llvm-svn: 82790
* Use getStoreSize() instead of getStoreSizeInBits()/8.Dan Gohman2009-09-231-1/+1
| | | | llvm-svn: 82656
* Remove BlackfinRegisterInfo::getFrameIndexOffset since it is the same as theBob Wilson2009-09-232-9/+0
| | | | | | | | default implementation. Update comment on the default version, which made it sound like most targets override it. Currently only X86 and SystemZ override this method. llvm-svn: 82651
* Tabs -> spaces, and remove trailing whitespace.Daniel Dunbar2009-09-201-2/+2
| | | | llvm-svn: 82355
* Remove unused variables.Daniel Dunbar2009-09-131-1/+0
| | | | llvm-svn: 81718
* remove all but one reference to TargetRegisterDesc::AsmName.Chris Lattner2009-09-131-1/+1
| | | | llvm-svn: 81714
* the tblgen produced 'getRegisterName' method does not accessChris Lattner2009-09-131-1/+1
| | | | | | the object, make it static instead of const. llvm-svn: 81711
* make tblgen produce a function that returns the name for a physreg.Chris Lattner2009-09-131-0/+2
| | | | | | Nothing is using this info yet. llvm-svn: 81707
* replace printBasicBlockLabel with EmitBasicBlockStart,Chris Lattner2009-09-131-1/+1
| | | | | | | now that printBasicBlockLabel is only used for starting a MBB. This allows elimination of a bunch of arguments. llvm-svn: 81684
* convert some uses of printBasicBlockLabel to use GetMBBSymbolChris Lattner2009-09-131-1/+2
| | | | | | instead. llvm-svn: 81677
* remove DebugLoc from MCInst and eliminate "Comment printing" fromChris Lattner2009-09-091-0/+6
| | | | | | | | | | | | | the MCInst path of the asmprinter. Instead, pull comment printing out of the autogenerated asmprinter into each target that uses the autogenerated asmprinter. This causes code duplication into each target, but in a way that will be easier to clean up later when more asmprinter stuff is commonized into the base AsmPrinter class. This also fixes an xcore strangeness where it inserted two tabs before every instruction. llvm-svn: 81396
* Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.Sandeep Patel2009-09-022-6/+6
| | | | llvm-svn: 80773
* Normalize makefile comments and sort cmake file lists.Benjamin Kramer2009-08-312-2/+2
| | | | llvm-svn: 80584
* eliminate the last DOUTs from the targets.Chris Lattner2009-08-231-1/+1
| | | | llvm-svn: 79833
* Forgot to update some CMakeLists.Benjamin Kramer2009-08-221-1/+1
| | | | llvm-svn: 79780
* rename TAI -> MAI, being careful not to make MAILJMP instructions :)Chris Lattner2009-08-221-7/+7
| | | | llvm-svn: 79777
* Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.Chris Lattner2009-08-224-14/+13
| | | | llvm-svn: 79763
* Record variable debug info at ISel time directly.Devang Patel2009-08-221-1/+0
| | | | llvm-svn: 79742
* eliminate AsmPrinter::SwitchToSection and just have clientsChris Lattner2009-08-191-2/+4
| | | | | | talk to the MCStreamer directly instead. llvm-svn: 79405
* Simplify RegScavenger::FindUnusedReg.Jakob Stoklund Olesen2009-08-181-1/+1
| | | | | | | | | - Drop the Candidates argument and fix all callers. Now that RegScavenger tracks available registers accurately, there is no need to restict the search. - Make sure that no aliases of the found register are in use. This was a potential bug. llvm-svn: 79369
* Change TargetAsmInfo to be constructed via TargetRegistry from a Target+TripleChris Lattner2009-08-124-9/+6
| | | | | | | | pair instead of from a virtual method on TargetMachine. This cuts the final ties of TargetAsmInfo to TargetMachine, meaning that MC can now use TargetAsmInfo. llvm-svn: 78802
* Move immediate constant predicate templates from the Blackfin target to ↵Jakob Stoklund Olesen2009-08-123-28/+18
| | | | | | MathExtras.h llvm-svn: 78793
* Change the asmprinter to print the comment character before theChris Lattner2009-08-111-2/+0
| | | | | | | | | | "inlineasmstart/end" strings so that the contents of the directive are separate from the comment character. This lets elf targets get #APP/#NOAPP for free even if they don't use "#" as the comment character. This also allows hoisting the darwin stuff up to the shared TAI class. llvm-svn: 78737
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-115-97/+97
| | | | | | | | while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
* pass the TargetTriple down from each target ctor to theChris Lattner2009-08-111-1/+1
| | | | | | LLVMTargetMachine ctor. It is currently unused. llvm-svn: 78711
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-106-105/+105
| | | | | | own struct type. llvm-svn: 78610
* Start moving TargetLowering away from using full MVTs and towards ↵Owen Anderson2009-08-102-2/+2
| | | | | | SimpleValueType, which will simplify the privatization of IntegerType in the future. llvm-svn: 78584
* Add support for READCYCLECOUNTER in Blackfin back-end.Jakob Stoklund Olesen2009-08-083-0/+35
| | | | llvm-svn: 78506
* make printInstruction return void since its result is omitted. Make the Chris Lattner2009-08-081-1/+1
| | | | | | error condition get trapped with an assert. llvm-svn: 78449
* Major calling convention code refactoring.Dan Gohman2009-08-052-66/+61
| | | | | | | | | | | | | | | | | | | Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
* Restlyize to match other targets, fixes cmake build to boot.Mike Stump2009-08-042-2/+7
| | | | llvm-svn: 78105
* Most flags are reserved registers on Blackfin.Jakob Stoklund Olesen2009-08-041-0/+11
| | | | | | The only exception is CC. llvm-svn: 78089
* Update CMake files.Ted Kremenek2009-08-032-0/+2
| | | | llvm-svn: 78020
* Minor stylistic cleanups in the Blackfin target.Jakob Stoklund Olesen2009-08-033-42/+46
| | | | | | Thanks Chris. llvm-svn: 77987
* Move most targets TargetMachine constructor to only taking a target triple.Daniel Dunbar2009-08-022-16/+3
| | | | | | - The C, C++, MSIL, and Mips backends still need the module. llvm-svn: 77927
* Normalize Subtarget constructors to take a target triple string instead ofDaniel Dunbar2009-08-023-8/+3
| | | | | | | | | | Module*. Also, dropped uses of TargetMachine where unnecessary. The only target which still takes a TargetMachine& is Mips, I would appreciate it if someone would normalize this to match other targets. llvm-svn: 77918
* Remove unneeded intrinsics from Blackfin backend.Jakob Stoklund Olesen2009-08-021-7/+1
| | | | | | | | | | __builtin_bfin_ones does the same as ctpop, so it can be implemented in the front-end. __builtin_bfin_loadbytes loads from an unaligned pointer with the disalignexcpt instruction. It does the same as loading from a pointer with the low bits masked. It is better if the front-end creates a masked load. We can always instruction select the masked to disalignexcpt+load. We keep csync/ssync/idle. These intrinsics represent instructions that need workarounds for some silicon revisions. We may even want to convert inline assembler to intrinsics to enable the workarounds. llvm-svn: 77917
* Add some basic blackfin intrinsics.Jakob Stoklund Olesen2009-08-021-1/+42
| | | | llvm-svn: 77903
* Add support for CPU features (i.e., bugs) and workarounds.Jakob Stoklund Olesen2009-08-024-8/+250
| | | | | | This is just the framework to identify the needed workarounds. They are not actually implemented. llvm-svn: 77902
* Inline assembly support for Blackfin.Jakob Stoklund Olesen2009-08-023-12/+137
| | | | | | We use the same constraints as GCC, including those that are slightly insane for inline assembler. llvm-svn: 77899
* Analog Devices Blackfin back-end.Jakob Stoklund Olesen2009-08-0228-0/+3787
Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. llvm-svn: 77897
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