| Commit message (Collapse) | Author | Age | Files | Lines |
| |
|
|
| |
llvm-svn: 108567
|
| |
|
|
| |
llvm-svn: 108366
|
| |
|
|
| |
llvm-svn: 108094
|
| |
|
|
| |
llvm-svn: 108077
|
| |
|
|
|
|
| |
code can do calling-convention queries. This obviates OutputArgReg.
llvm-svn: 107786
|
| |
|
|
| |
llvm-svn: 107710
|
| |
|
|
|
|
| |
slots so it's always false.
llvm-svn: 107550
|
| |
|
|
| |
llvm-svn: 106457
|
| |
|
|
|
|
| |
SDNode *, since it doesn't care about the ResNo value.
llvm-svn: 106282
|
| |
|
|
|
|
|
|
|
|
|
|
| |
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.
This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.
llvm-svn: 106243
|
| |
|
|
| |
llvm-svn: 105322
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
llvm-svn: 104704
|
| |
|
|
|
|
| |
This reverts commit 104654.
llvm-svn: 104660
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
llvm-svn: 104654
|
| |
|
|
|
|
|
| |
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.
llvm-svn: 104627
|
| |
|
|
| |
llvm-svn: 104571
|
| |
|
|
|
|
|
|
|
|
|
| |
structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
llvm-svn: 104563
|
| |
|
|
|
|
|
| |
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.
llvm-svn: 104492
|
| |
|
|
|
|
|
|
|
| |
the variable actually tracks.
N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.
llvm-svn: 103802
|
| |
|
|
|
|
|
|
| |
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.
llvm-svn: 103481
|
| |
|
|
|
|
| |
doesn't have to guess.
llvm-svn: 103194
|
| |
|
|
| |
llvm-svn: 103193
|
| |
|
|
|
|
|
| |
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181
llvm-svn: 101984
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
llvm-svn: 101635
|
| |
|
|
|
|
| |
MachineFunctionInfo subclasses.
llvm-svn: 101634
|
| |
|
|
| |
llvm-svn: 101564
|
| |
|
|
| |
llvm-svn: 101334
|
| |
|
|
| |
llvm-svn: 100399
|
| |
|
|
|
|
|
|
|
|
| |
"asm printering" happens through MCStreamer. This also
Streamerizes PIC16 debug info, which escaped my attention.
This removes a leak from LLVMTargetMachine of the 'legacy'
output stream.
llvm-svn: 100327
|
| |
|
|
|
|
|
| |
implementations to use EmitRawText instead of writing
directly to "O".
llvm-svn: 100318
|
| |
|
|
|
|
| |
raw_ostream to print to.
llvm-svn: 100313
|
| |
|
|
|
|
| |
member of AsmPrinter. Instead, pass it in explicitly.
llvm-svn: 100306
|
| |
|
|
|
|
| |
of printOffset to pass in a stream to print to.
llvm-svn: 100296
|
| |
|
|
| |
llvm-svn: 100214
|
| |
|
|
|
|
|
| |
makes calls a little bit more consistent and allows easy removal of the
specializations in the future. Convert all callers to the templated functions.
llvm-svn: 99838
|
| |
|
|
|
|
| |
just use an empty result list.
llvm-svn: 99346
|
| |
|
|
|
|
| |
Thanks, Chris!
llvm-svn: 99183
|
| |
|
|
|
|
| |
need them.
llvm-svn: 98937
|
| |
|
|
|
|
| |
match. Jakob, please take a look when you get a chance.
llvm-svn: 98931
|
| |
|
|
|
|
|
|
| |
intrinsics. The intrinsic lookup code assumes that this check has been done
and assumes the names are at least 6 characters long. Valgrind complained
about this. pr6638.
llvm-svn: 98831
|
| |
|
|
| |
llvm-svn: 98451
|
| |
|
|
|
|
|
|
|
|
|
| |
and passing off ownership to AsmPrinter. Now MachineModuleInfo
creates it and owns it by value. This allows us to use MCSymbols
more consistently throughout the rest of the code generator, and
simplifies a bit of code. This also allows MachineFunction to
keep an MCContext reference handy, and cleans up the TargetRegistry
interfaces for AsmPrinters.
llvm-svn: 98450
|
| |
|
|
| |
llvm-svn: 98394
|
| |
|
|
|
|
| |
remove it.
llvm-svn: 98390
|
| |
|
|
|
|
|
|
|
|
| |
is preparatory to having PEI's scavenged frame index value reuse logic
properly distinguish types of frame values (e.g., whether the value is
stack-pointer relative or frame-pointer relative).
No functionality change.
llvm-svn: 98086
|
| |
|
|
|
|
|
|
|
|
|
|
| |
DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.
Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.
17 files changed, 114 insertions(+), 430 deletions(-)
llvm-svn: 97555
|
| |
|
|
| |
llvm-svn: 96288
|
| |
|
|
|
|
| |
change to SelectionDAG build APIs.
llvm-svn: 96231
|
| |
|
|
|
|
| |
OutStreamer.AddBlankLine instead of textually.
llvm-svn: 95734
|
| |
|
|
|
|
|
|
|
| |
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
llvm-svn: 95687
|