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path: root/llvm/lib/Target/Alpha/AlphaInstrFormats.td
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* Remove the Alpha backend.Dan Gohman2011-10-271-268/+0
| | | | llvm-svn: 143164
* Remove isTwoAddress from Alpha.Eric Christopher2010-06-211-2/+2
| | | | llvm-svn: 106445
* use ins/outs.Chris Lattner2010-03-181-10/+10
| | | | llvm-svn: 98866
* Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman2008-12-031-1/+1
| | | | llvm-svn: 60487
* llvm.memory.barrier, and impl for x86 and alphaAndrew Lenharth2008-02-161-0/+8
| | | | llvm-svn: 47204
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-1/+1
| | | | llvm-svn: 45667
* Change the 'isStore' inferrer to look for 'SDNPMayStore' Chris Lattner2008-01-061-2/+1
| | | | | | | | | | | instead of "ISD::STORE". This allows us to mark target-specific dag nodes as storing (such as ppc byteswap stores). This allows us to remove more explicit isStore flags from the .td files. Finally, add a warning for when a .td file contains an explicit isStore and tblgen is able to infer it. llvm-svn: 45654
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* No more noResults.Evan Cheng2007-07-211-1/+1
| | | | llvm-svn: 40132
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-13/+25
| | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
* Use this nifty Constraints thing and fix the inverted conditional movesAndrew Lenharth2007-04-171-7/+11
| | | | llvm-svn: 36191
* Add all that branch mangling niftinessAndrew Lenharth2006-10-311-19/+9
| | | | llvm-svn: 31313
* Let the alpha breakage begin. First Formals and RET. next CallsAndrew Lenharth2006-06-121-0/+14
| | | | llvm-svn: 28753
* Alpha Scheduling classesAndrew Lenharth2006-03-091-33/+44
| | | | llvm-svn: 26643
* Add immediate forms of cmov and remove some cruftAndrew Lenharth2006-02-011-3/+5
| | | | llvm-svn: 25882
* minor renamingAndrew Lenharth2006-01-261-1/+1
| | | | llvm-svn: 25640
* allow R28 to be used for frame calculations without entirely removing it ↵Andrew Lenharth2006-01-261-18/+1
| | | | | | from circulation llvm-svn: 25639
* stack and rpccAndrew Lenharth2006-01-161-3/+2
| | | | llvm-svn: 25369
* Move brcond over and fix some imm patterns. This may be the last change ↵Andrew Lenharth2006-01-011-2/+15
| | | | | | before changing the default alpha isel. llvm-svn: 25057
* add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAGAndrew Lenharth2005-12-251-3/+6
| | | | llvm-svn: 25011
* Unify the patterns for loads and stores. Now offset addressing should beAndrew Lenharth2005-12-241-22/+3
| | | | | | supported. This almost completes memory operations. llvm-svn: 25002
* move loads and stores over. Smart addr selection commingAndrew Lenharth2005-12-241-0/+12
| | | | llvm-svn: 25000
* OK, this does wonders for broken stuffAndrew Lenharth2005-12-061-0/+1
| | | | llvm-svn: 24624
* added instructions with inverted immediatesAndrew Lenharth2005-12-061-17/+1
| | | | llvm-svn: 24614
* These never trigger, but whateverAndrew Lenharth2005-12-051-0/+18
| | | | llvm-svn: 24612
* All sorts of stuff.Andrew Lenharth2005-11-301-0/+10
| | | | | | | | | | | | | Getting in on the custom lowering thing, yay evilness with fp setcc, yuck trivial int select, hmmm in memory args for functions, yay DIV and REM, always handy. They should be custom lowered though. Lots more stuff compiles now (go go single source!). Of course, none of it probably works, but that is what the nightly tester can find out :) llvm-svn: 24533
* massive DAGISel patch. lots and lots more stuff compiles nowAndrew Lenharth2005-11-221-1/+3
| | | | llvm-svn: 24483
* continued readcyclecounter supportAndrew Lenharth2005-11-111-0/+9
| | | | llvm-svn: 24300
* whatever. Intermediate patch to see what breaks. Seems ok.Andrew Lenharth2005-11-091-21/+11
| | | | llvm-svn: 24260
* Simplify instinfo, set random bits on more fp insts, and fix 1 opcodeAndrew Lenharth2005-10-261-2/+3
| | | | llvm-svn: 24014
* Well, the Constant matching pattern works. Can't say much about calls or ↵Andrew Lenharth2005-10-221-1/+9
| | | | | | globals yet. llvm-svn: 23884
* Inst cleanup. As a bonus, operands are in the correct order for cmovs. ↵Andrew Lenharth2005-10-201-9/+11
| | | | | | Expect new stuff to pass in the JIT tonight llvm-svn: 23852
* added a few 1 operand form stuff. Seems to break regalloc on alpha. sighAndrew Lenharth2005-10-201-0/+16
| | | | llvm-svn: 23849
* ret 0; works, not much elseAndrew Lenharth2005-10-201-6/+10
| | | | | | | | still lots of uglyness. Maybe calls will come soon. Fixing the return value of things will be necessary to make alpha work. llvm-svn: 23832
* support bsr, and more .td simplificationAndrew Lenharth2005-07-281-1/+15
| | | | llvm-svn: 22543
* simpilfy instruction encoding (and make the lines way shorter, aka Misha ↵Andrew Lenharth2005-07-221-6/+76
| | | | | | happification) llvm-svn: 22499
* Make the rest of file header comments consistent in format and styleMisha Brukman2005-02-051-1/+1
| | | | llvm-svn: 20048
* initial fp supportAndrew Lenharth2005-01-261-2/+2
| | | | llvm-svn: 19847
* Clean ups, and taught the instruction selector about immediate formsAndrew Lenharth2005-01-241-3/+2
| | | | llvm-svn: 19816
* Let me introduce you to the early stages of the llvm backend for the alpha ↵Andrew Lenharth2005-01-221-0/+109
processor llvm-svn: 19764
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