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* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-153-5/+5
| | | | | | The Function can never be nullptr so we can return a reference. llvm-svn: 320884
* [AVR] Implement some missing code pathsDylan McKay2017-12-112-4/+19
| | | | | | This has been broken since r320009. llvm-svn: 320348
* [AVR] Fix incorrectly-calculated AVRMCExpr evaluationsDylan McKay2017-12-111-12/+9
| | | | | | This has been broken since r320009. llvm-svn: 320347
* Revert and accidentally committed revert commitDylan McKay2017-12-0911-22/+275
| | | | | | This reverts commit r320245. llvm-svn: 320247
* Revert "[AVR] Override ParseDirective"Dylan McKay2017-12-0911-275/+22
| | | | | | This reverts commit 57c16f9267969ebb09d6448607999b4a9f40c418. llvm-svn: 320245
* Relax unaligned access assertion when type is byte alignedDylan McKay2017-12-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This relaxes an assertion inside SelectionDAGBuilder which is overly restrictive on targets which have no concept of alignment (such as AVR). In these architectures, all types are aligned to 8-bits. After this, LLVM will only assert that accesses are aligned on targets which actually require alignment. This patch follows from a discussion on llvm-dev a few months ago http://llvm.1065342.n5.nabble.com/llvm-dev-Unaligned-atomic-load-store-td112815.html Reviewers: bogner, nemanjai, joerg, efriedma Reviewed By: efriedma Subscribers: efriedma, cactus, llvm-commits Differential Revision: https://reviews.llvm.org/D39946 llvm-svn: 320243
* [AVR] Override ParseDirectiveLeslie Zhai2017-12-0711-22/+275
| | | | | | | | | | Reviewers: dylanmckay, kparzysz Reviewed By: dylanmckay Differential Revision: https://reviews.llvm.org/D38029 llvm-svn: 320009
* Add backend name to AVR Target to enable runtime info to be fed back into ↵Leslie Zhai2017-11-231-1/+1
| | | | | | TableGen llvm-svn: 318895
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-176-7/+7
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
| | | | | | | | This header includes CodeGen headers, and is not, itself, included by any Target headers, so move it into CodeGen to match the layering of its implementation. llvm-svn: 317647
* Move TargetFrameLowering.h to CodeGen where it's implementedDavid Blaikie2017-11-032-2/+2
| | | | | | | | | | | This header already includes a CodeGen header and is implemented in lib/CodeGen, so move the header there to match. This fixes a link error with modular codegeneration builds - where a header and its implementation are circularly dependent and so need to be in the same library, not split between two like this. llvm-svn: 317379
* [AVR] Update to current LLVM APIDylan McKay2017-10-185-9/+19
| | | | | | | r315410 broke a number of things in the AVR backend, which are now fixed. llvm-svn: 316076
* Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine"Matthias Braun2017-10-122-4/+6
| | | | | | | | | | Reverting to investigate layering effects of MCJIT not linking libCodeGen but using TargetMachine::getNameWithPrefix() breaking the lldb bots. This reverts commit r315633. llvm-svn: 315637
* TargetMachine: Merge TargetMachine and LLVMTargetMachineMatthias Braun2017-10-122-6/+4
| | | | | | | | | | | | | | | Merge LLVMTargetMachine into TargetMachine. - There is no in-tree target anymore that just implements TargetMachine but not LLVMTargetMachine. - It should still be possible to stub out all the various functions in case a target does not want to use lib/CodeGen - This simplifies the code and avoids methods ending up in the wrong interface. Differential Revision: https://reviews.llvm.org/D38489 llvm-svn: 315633
* [Asm] Add debug tracing in table-generated assembly matcherOliver Stannard2017-10-111-1/+1
| | | | | | | | | | | | | This adds debug tracing to the table-generated assembly instruction matcher, enabled by the -debug-only=asm-matcher option. The changes in the target AsmParsers are to add an MCInstrInfo reference under a consistent name, so that we can use it from table-generated code. This was already being used this way for targets that use deprecation warnings, but 5 targets did not have it, and Hexagon had it under a different name to the other backends. llvm-svn: 315445
* [AVR] Implement LPMWRdZ pseudo-instruction's expansion.Dylan McKay2017-10-041-1/+44
| | | | | | | | | FIXME: implementation is mostly copy-pasted from LDWRdPtr, so we should refactor a bit and unify the two Patch by Gerdo Erdi. llvm-svn: 314898
* [AVR] Factor out mayLoad in tablegen patternsDylan McKay2017-10-041-2/+2
| | | | | | Patch by Gergo Erdi. llvm-svn: 314897
* [AVR] Elaborate LDWRdPtr into `ld r, X++; ld r+1, X`Dylan McKay2017-10-042-7/+7
| | | | | | Patch by Gergo Erdi. llvm-svn: 314896
* [AVR] Insert JMP for long branchesDylan McKay2017-10-042-2/+22
| | | | | | | | | | | Previously, on long branches (relative jumps of >4 kB), an assertion failure was hit, as AVRInstrInfo::insertIndirectBranch was not implemented. Despite its name, it is called by the branch relaxator for *all* unconditional jumps. Patch by Thomas Backman. llvm-svn: 314891
* [AVR] Fix displacement overflow for LDDW/STDWDylan McKay2017-10-042-5/+13
| | | | | | | | | | | | | | | | | | | In some cases, the code generator attempts to generate instructions such as: lddw r24, Y+63 which expands to: ldd r24, Y+63 ldd r25, Y+64 # Oops! This is actually ld r25, Y in the binary This commit limits the first offset to 62, and thus the second to 63. It also updates some asserts in AVRExpandPseudoInsts.cpp, including for INW and OUTW, which appear to be unused. Patch by Thomas Backman. llvm-svn: 314890
* [AVR] Prefer BasicBlock::getIterator over Function::begin()Dylan McKay2017-09-261-1/+1
| | | | | | Thanks to Eli Friedman for the suggestion. llvm-svn: 314182
* [AVR] When lowering shifts into loops, put newly generated MBBs in the sameDylan McKay2017-09-261-2/+4
| | | | | | | | | | | spot as the original MBB Discovered in avr-rust/rust#62 https://github.com/avr-rust/rust/issues/62 Patch by Gergo Erdi. llvm-svn: 314180
* [AVR] Use 1-byte alignment for all data typesDylan McKay2017-09-261-1/+1
| | | | | | | | | | | | | | This was an oversight in the original backend data layout. The AVR architecture does not have the concept of unaligned loads - all loads/stores from all addresses are aligned to one byte. Discovered in avr-rust issue #64 https://github.com/avr-rust/rust/issues/64 Patch By Gergo Erdi. llvm-svn: 314179
* [AVR] Implement getCmpLibcallReturnType().Dylan McKay2017-09-241-0/+5
| | | | | | | | | This fixes the avr-rust issue (#75) with floating-point comparisons generating broken code. By default, LLVM assumes these comparisons return 32-bit values, but ours are 8-bit. Patch By Thomas Backman. llvm-svn: 314070
* [AVR] Remove the 'IsN64' argument to 'MCELFObjectWriter'Dylan McKay2017-09-221-1/+1
| | | | | | This has since been removed. llvm-svn: 313965
* [AVR] Enable the '__do_copy_data' functionDylan McKay2017-09-112-0/+22
| | | | | | | | | | | | | Also enables '__do_clear_bss'. These functions are automaticalled called by the CRT if they are declared. We need these to be called otherwise RAM will start completely uninitialised, even though we need to copy RAM variables from progmem to RAM. llvm-svn: 312905
* [AVR] Use the correct register classes for 16-bit atomic operationsDylan McKay2017-08-241-22/+42
| | | | llvm-svn: 311620
* Add "Restored" flag to CalleeSavedInfoKrzysztof Parzyszek2017-08-102-2/+2
| | | | | | | | | | | The liveness-tracking code assumes that the registers that were saved in the function's prolog are live outside of the function. Specifically, that registers that were saved are also live-on-exit from the function. This isn't always the case as illustrated by the LR register on ARM. Differential Revision: https://reviews.llvm.org/D36160 llvm-svn: 310619
* [AVR] Compute code model if one is not providedMeador Inge2017-08-061-6/+10
| | | | | | | | | | | | | | The patch from r310028 fixed things to work with the new `LLVMTargetMachine` constructor that came in on r309911. However, the fix was partial since an object of type `CodeModel::Model` must be passed to `LLVMTargetMachine` (not one of `Optional<CodeModel::Model>`). This patch fixes the problem in the same fashion that r309911 did for other machines: by checking if the passed optional code model has a value and using `CodeModel::Small` if not. llvm-svn: 310200
* [AVR] Update target machine to use new constructor parametersDylan McKay2017-08-042-5/+10
| | | | | | The required parameters were changed in r309911. llvm-svn: 310028
* [AVR] Remove the instrumentation passDylan McKay2017-07-234-226/+0
| | | | | | | | I have a much better way of running integration tests now. https://github.com/dylanmckay/avr-test-suite llvm-svn: 308857
* [SystemZ, LoopStrengthReduce]Jonas Paulsson2017-07-212-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes LSR generate better code for SystemZ in the cases of memory intrinsics, Load->Store pairs or comparison of immediate with memory. In order to achieve this, the following common code changes were made: * New TTI hook: LSRWithInstrQueries(), which defaults to false. Controls if LSR should do instruction-based addressing evaluations by calling isLegalAddressingMode() with the Instruction pointers. * In LoopStrengthReduce: handle address operands of memset, memmove and memcpy as address uses, and call isFoldableMemAccessOffset() for any LSRUse::Address, not just loads or stores. SystemZ changes: * isLSRCostLess() implemented with Insns first, and without ImmCost. * New function supportedAddressingMode() that is a helper for TTI methods looking at Instructions passed via pointers. Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D35262 https://reviews.llvm.org/D35049 llvm-svn: 308729
* [AVR] Fix broken indentationDylan McKay2017-07-131-1/+1
| | | | llvm-svn: 307891
* [AVR] Add a 'LLVM_FALLTHROUGH' statement to the AsmParserDylan McKay2017-07-131-0/+1
| | | | | | Should fix warnings in the build. llvm-svn: 307890
* [AVR] Fix indirect calls to function pointersDylan McKay2017-07-131-2/+14
| | | | | | Patch by Carl Peto. llvm-svn: 307888
* [AVR] Remove a few very old TODOs that don't have enough context to understandDylan McKay2017-07-112-3/+4
| | | | llvm-svn: 307622
* [AVR] Rename 'ZREGS' to 'ZREG'Dylan McKay2017-07-113-16/+13
| | | | | | It will only ever contain one register. llvm-svn: 307620
* [AVR] Rename 'AVRTiny' to 'Tiny'Dylan McKay2017-07-112-13/+12
| | | | llvm-svn: 307619
* [AVR] Use the generic branch relaxerDylan McKay2017-07-113-5/+77
| | | | llvm-svn: 307617
* Revert "[AVR] Add the branch selection pass from the GitHub repository"Dylan McKay2017-07-053-269/+0
| | | | | | This reverts commit 602ef067c1d58ecb425d061f35f2bc4c7e92f4f3. llvm-svn: 307111
* [AVR] Add the branch selection pass from the GitHub repositoryDylan McKay2017-07-053-0/+269
| | | | | | | We should rewrite this using the generic branch relaxation pass, but for the moment having this pass is better than hitting an assertion error. llvm-svn: 307109
* [AVR] Fix bug which caused assertion errors for some FRMIDX instructionsDylan McKay2017-07-041-3/+8
| | | | | | | | | | | | | Previously, if a basic block ended with a FRMIDX instruction, we would end up doing something like this. *std::next(MBB.end()) Which would hit an error: "Assertion `!NodePtr->isKnownSentinel()' failed." llvm-svn: 307057
* [AVR] Add a missing clobber declaration to LPMWDylan McKay2017-07-041-6/+6
| | | | llvm-svn: 307056
* [AVR] Update AVRASmBackend from API change in r306906Dylan McKay2017-07-012-7/+7
| | | | llvm-svn: 306923
* [AVR] Migrate to new MCAsmBackend applyFixup and processFixupValueLeslie Zhai2017-06-272-28/+26
| | | | | | | | | | | | Reviewers: rafael, dylanmckay, jroelofs, meadori Reviewed By: rafael, meadori Subscribers: meadori, llvm-commits Differential Revision: https://reviews.llvm.org/D34551 llvm-svn: 306359
* Fix -Wunused-variable.Rui Ueyama2017-06-091-2/+0
| | | | llvm-svn: 305051
* Move Object format code to lib/BinaryFormat.Zachary Turner2017-06-073-3/+3
| | | | | | | | | | | | This creates a new library called BinaryFormat that has all of the headers from llvm/Support containing structure and layout definitions for various types of binary formats like dwarf, coff, elf, etc as well as the code for identifying a file from its magic. Differential Revision: https://reviews.llvm.org/D33843 llvm-svn: 304864
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-068-13/+12
| | | | | | | | | | | | | | | | | | | | | | | | | I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
* TargetMachine: Indicate whether machine verifier passes.Matthias Braun2017-05-311-0/+4
| | | | | | | | | | | | | This adds a callback to the LLVMTargetMachine that lets target indicate that they do not pass the machine verifier checks in all cases yet. This is intended to be a temporary measure while the targets are fixed allowing us to enable the machine verifier by default with EXPENSIVE_CHECKS enabled! Differential Revision: https://reviews.llvm.org/D33696 llvm-svn: 304320
* [AVR] Fix a big in shift operator lowering; Authored by Dr. Gergo ErdiDylan McKay2017-05-311-2/+2
| | | | | | | When generating code for a shift loop, check the shift amount against the literal value 0, not R0 llvm-svn: 304284
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