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| author | Dylan McKay <me@dylanmckay.io> | 2017-07-11 05:14:40 +0000 |
|---|---|---|
| committer | Dylan McKay <me@dylanmckay.io> | 2017-07-11 05:14:40 +0000 |
| commit | 946ab551edefd28476e98d9a933ba46e1f976a3d (patch) | |
| tree | 39915ed7164fed48d3634cfa3f12b27f1608105d /llvm/lib/Target/AVR | |
| parent | a36eae0b2be9fe3b8f06f36e22975fa757364fca (diff) | |
| download | bcm5719-llvm-946ab551edefd28476e98d9a933ba46e1f976a3d.tar.gz bcm5719-llvm-946ab551edefd28476e98d9a933ba46e1f976a3d.zip | |
[AVR] Remove a few very old TODOs that don't have enough context to understand
llvm-svn: 307622
Diffstat (limited to 'llvm/lib/Target/AVR')
| -rw-r--r-- | llvm/lib/Target/AVR/AVRAsmPrinter.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/AVR/AVRRegisterInfo.td | 2 |
2 files changed, 4 insertions, 3 deletions
diff --git a/llvm/lib/Target/AVR/AVRAsmPrinter.cpp b/llvm/lib/Target/AVR/AVRAsmPrinter.cpp index f0c7b11895b..c058c9e1f53 100644 --- a/llvm/lib/Target/AVR/AVRAsmPrinter.cpp +++ b/llvm/lib/Target/AVR/AVRAsmPrinter.cpp @@ -149,7 +149,10 @@ bool AVRAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, (void)MO; assert(MO.isReg() && "Unexpected inline asm memory operand"); - // TODO: We can look up the alternative name for the register if it's given. + // TODO: We should be able to look up the alternative name for + // the register if it's given. + // TableGen doesn't expose a way of getting retrieving names + // for registers. if (MI->getOperand(OpNum).getReg() == AVR::R31R30) { O << "Z"; } else { diff --git a/llvm/lib/Target/AVR/AVRRegisterInfo.td b/llvm/lib/Target/AVR/AVRRegisterInfo.td index 8d663637a2b..8162f12052b 100644 --- a/llvm/lib/Target/AVR/AVRRegisterInfo.td +++ b/llvm/lib/Target/AVR/AVRRegisterInfo.td @@ -202,8 +202,6 @@ def ZREG : RegisterClass<"AVR", [i16], 8, (add R31R30)>; // Register class used for the stack read pseudo instruction. def GPRSP: RegisterClass<"AVR", [i16], 8, (add SP)>; -//:TODO: if we remove this we get an error in tablegen -//:TODO: this is just a hack, remove it once add16 works! // Status register. def SREG : AVRReg<14, "FLAGS">, DwarfRegNum<[88]>; def CCR : RegisterClass<"AVR", [i8], 8, (add SREG)> |
