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path: root/llvm/lib/Target/AVR/AVRTargetMachine.cpp
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* [AVR] Add a function instrumentation passDylan McKay2016-12-141-0/+1
| | | | | | This will be used for an on-chip test suite. llvm-svn: 289641
* [AVR] Add an 'relax memory operation' passDylan McKay2016-12-131-1/+5
| | | | | | | | | | | | | | | | | | | | | | Summary: This pass will be used to relax instructions which use out of bounds memory accesses to equivalent operations that can work with the addresses. The pass currently implements relaxation for the STDWPtrQRr instruction. Without this pass, an assertion error would be hit in the pseudo expansion pass. In the future, we will need to add more instructions to this pass. We can do that on a case-by-case basic. Reviewers: arsenm, kparzysz Subscribers: wdng, llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D27650 llvm-svn: 289517
* [AVR] Allow loading from stack slots where src and dest registers are identicalDylan McKay2016-12-071-0/+3
| | | | | | Fixes PR 31256 llvm-svn: 288897
* [AVR] Remove unused method from AVRTargetMachineDylan McKay2016-11-161-3/+0
| | | | llvm-svn: 287173
* [AVR] Add the pseudo instruction expansion passDylan McKay2016-11-161-1/+1
| | | | | | | | | | | | | | | | | | Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 llvm-svn: 287162
* [AVR] Enable the ISel, frame analyzer, and alloca passesDylan McKay2016-11-071-2/+8
| | | | llvm-svn: 286095
* Move the global variables representing each Target behind accessor functionMehdi Amini2016-10-091-1/+1
| | | | | | | | This avoids "static initialization order fiasco" Differential Revision: https://reviews.llvm.org/D25412 llvm-svn: 283702
* [AVR] Update the data layoutDylan McKay2016-09-281-1/+3
| | | | | | | | | | | | | | | The previous data layout caused issues when dealing with atomics. Foe example, it is illegal to load a 16-bit value with less than 16-bits of alignment. This changes the data layout so that all types are aligned by at least their own width. Interestingly, this also _slightly_ decreased register pressure in some cases. llvm-svn: 282587
* [AVR] Fix signuature of AVRTargetMachine constructorDylan McKay2016-05-201-2/+6
| | | | llvm-svn: 270292
* [AVR] Fix a few compile errorsDylan McKay2016-05-181-3/+3
| | | | llvm-svn: 269900
* CodeGen: Move TargetPassConfig from Passes.h to an own header; NFCMatthias Braun2016-05-101-0/+1
| | | | | | | | Many files include Passes.h but only a fraction needs to know about the TargetPassConfig class. Move it into an own header. Also rename Passes.cpp to TargetPassConfig.cpp while we are at it. llvm-svn: 269011
* [AVR] Add a majority of the backend codeDylan McKay2016-05-061-0/+96
| | | | | | | | | | | | Summary: This adds the majority of the AVR backend. Reviewers: hfinkel, dsanders, vkalintiris, arsenm Subscribers: dylanmckay Differential Revision: http://reviews.llvm.org/D17906 llvm-svn: 268722
* Add AVR backend skeletonDylan McKay2015-11-121-0/+4
This adds part of the target info code, and adds modifications to the build scripts so that AVR is recognized a supported, experimental backend. It does not include any AVR-specific code, just the bare sources required for a backend to exist. From D14039. llvm-svn: 252865
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