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| author | Dylan McKay <dylanmckay34@gmail.com> | 2016-09-28 13:29:10 +0000 |
|---|---|---|
| committer | Dylan McKay <dylanmckay34@gmail.com> | 2016-09-28 13:29:10 +0000 |
| commit | b967d16c4319aa46d480e184624153df3828c9fb (patch) | |
| tree | 748ab14af0d1d91f964979b2d49afc6aad8c33f9 /llvm/lib/Target/AVR/AVRTargetMachine.cpp | |
| parent | 35047ed7416d53b32a71ea98e802e3e29adfe350 (diff) | |
| download | bcm5719-llvm-b967d16c4319aa46d480e184624153df3828c9fb.tar.gz bcm5719-llvm-b967d16c4319aa46d480e184624153df3828c9fb.zip | |
[AVR] Update the data layout
The previous data layout caused issues when dealing with atomics.
Foe example, it is illegal to load a 16-bit value with less than 16-bits
of alignment.
This changes the data layout so that all types are aligned by at least
their own width.
Interestingly, this also _slightly_ decreased register pressure in some
cases.
llvm-svn: 282587
Diffstat (limited to 'llvm/lib/Target/AVR/AVRTargetMachine.cpp')
| -rw-r--r-- | llvm/lib/Target/AVR/AVRTargetMachine.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.cpp b/llvm/lib/Target/AVR/AVRTargetMachine.cpp index 508723e91c6..b613c3a2f70 100644 --- a/llvm/lib/Target/AVR/AVRTargetMachine.cpp +++ b/llvm/lib/Target/AVR/AVRTargetMachine.cpp @@ -25,6 +25,8 @@ namespace llvm { +static const char *AVRDataLayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-n8"; + /// Processes a CPU name. static StringRef getCPU(StringRef CPU) { if (CPU.empty() || CPU == "generic") { @@ -44,7 +46,7 @@ AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT, Optional<Reloc::Model> RM, CodeModel::Model CM, CodeGenOpt::Level OL) : LLVMTargetMachine( - T, "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-i64:8:8-f32:8:8-f64:8:8-n8", TT, + T, AVRDataLayout, TT, getCPU(CPU), FS, Options, getEffectiveRelocModel(RM), CM, OL), SubTarget(TT, getCPU(CPU), FS, *this) { this->TLOF = make_unique<AVRTargetObjectFile>(); |
