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* Fix the ARM IIC_iCMPsi itinerary and add an important assert.Andrew Trick2011-01-042-1/+3
| | | | llvm-svn: 122794
* Formatting changes. No functionality change.Bill Wendling2011-01-031-80/+77
| | | | llvm-svn: 122789
* Model operand restrictions of mul-like instructions on ARMv5 viaAnton Korobeynikov2011-01-014-10/+100
| | | | | | | | | earlyclobber stuff. This should fix PRs 2313 and 8157. Unfortunately, no testcase, since it'd be dependent on register assignments. llvm-svn: 122663
* CMake: Add disabling optimization on MSVC8 and MSVC10 as workaround for some ↵NAKAMURA Takumi2010-12-292-2/+10
| | | | | | files in Target/ARM and Target/X86. llvm-svn: 122623
* Various bits of framework needed for precise machine-level selectionAndrew Trick2010-12-246-16/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. llvm-svn: 122541
* whitespaceAndrew Trick2010-12-244-5/+5
| | | | llvm-svn: 122539
* Use a StringSwitch<> instead of a manually constructed string matcher.Jim Grosbach2010-12-241-10/+7
| | | | llvm-svn: 122530
* Remove dead patterns.Jim Grosbach2010-12-231-26/+0
| | | | llvm-svn: 122524
* Recognize a few more documented register name aliases for ARM in the asm lexer.Jim Grosbach2010-12-231-0/+18
| | | | llvm-svn: 122523
* Radar 8803471: Fix expansion of ARM BCCi64 pseudo instructions.Bob Wilson2010-12-231-0/+3
| | | | | | | | If the basic block containing the BCCi64 (or BCCZi64) instruction ends with an unconditional branch, that branch needs to be deleted before appending the expansion of the BCCi64 to the end of the block. llvm-svn: 122521
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-233-19/+19
| | | | llvm-svn: 122513
* Trailing whitespace.Jim Grosbach2010-12-221-15/+15
| | | | llvm-svn: 122456
* Add ARM-specific DAG combining to cast i64 vector element load/stores to f64.Bob Wilson2010-12-211-5/+103
| | | | | | | | | | | Type legalization splits up i64 values into pairs of i32 values, which leads to poor quality code when inserting or extracting i64 vector elements. If the vector element is loaded or stored, it can be treated as an f64 value and loaded or stored directly from a VPR register. Use the pre-legalization DAG combiner to cast those vector elements to f64 types so that the type legalizer won't mess them up. Radar 8755338. llvm-svn: 122319
* Arm and thumb call instructions are also in different orders.Eric Christopher2010-12-211-13/+24
| | | | | | Fixes rdar://8782223 llvm-svn: 122313
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-212-10/+10
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* If we're not using reg+reg offset we're using reg+imm, set the opcodeEric Christopher2010-12-211-2/+2
| | | | | | | | | to be the one we want to use. bugpoint reduced testcase is a little large, I'll see if I can simplify it down more. Fixes part of rdar://8782207 llvm-svn: 122307
* Fix a copy-pasto. When the tBR_JTr instruction was converted to using theBill Wendling2010-12-211-1/+1
| | | | | | | | | tPseudoInst class, its size was changed from "special" to "2 bytes". This is incorrect because the jump table will no longer be taken into account when calculating branch offsets. <rdar://problem/8782216> llvm-svn: 122303
* Comment cleanups.Bill Wendling2010-12-211-2/+2
| | | | llvm-svn: 122302
* Remove the MCObjectFormat class.Rafael Espindola2010-12-181-12/+0
| | | | llvm-svn: 122147
* Move some data to the TargetWriter.Rafael Espindola2010-12-181-6/+5
| | | | llvm-svn: 122134
* r120333 changed the opcode for the Thumb1 stuff from ARM::tMOVr toBill Wendling2010-12-181-1/+1
| | | | | | | | | | | ARM::tMOVgpr2gpr. But this check didn't change. As a result, we were getting misaligned references to the jump table from an ADR instruction. There is a test case, but unfortunately it's sensitive to random code changes. <rdar://problem/8782223> llvm-svn: 122131
* RemoveUnusedCPEntries can change things. Track it.Bill Wendling2010-12-181-1/+1
| | | | llvm-svn: 122129
* Rearrange some Neon multiclasses. No functional changes.Bob Wilson2010-12-181-74/+76
| | | | llvm-svn: 122119
* Fix result type of Neon floating-point comparisons against zero.Bob Wilson2010-12-181-2/+2
| | | | | | The result vector elements are always integers. Radar 8782191. llvm-svn: 122112
* Add some missing entries in ARMTargetLowering::getTargetNodeName.Bob Wilson2010-12-181-0/+5
| | | | llvm-svn: 122111
* During local stack slot allocation, the materializeFrameBaseRegister functionBill Wendling2010-12-172-8/+14
| | | | | | | | | | | | | | | may be called. If the entry block is empty, the insertion point iterator will be the "end()" value. Calling ->getParent() on it (among others) causes problems. Modify materializeFrameBaseRegister to take the machine basic block and insert the frame base register at the beginning of that block. (It's very similar to what the code does all ready. The only difference is that it will always insert at the beginning of the entry block instead of after a previous materialization of the frame base register. I doubt that that matters here.) <rdar://problem/8782198> llvm-svn: 122104
* Avoid report_fatal_error in ARM's PrintAsmOperand method.Bob Wilson2010-12-171-1/+1
| | | | | | | The standard error handling in AsmPrinter::EmitInlineAsm handles this much better, so just use it. llvm-svn: 122100
* If The ARM WriteNopData() gets an unaligned byte count to pad out, fill in withJim Grosbach2010-12-171-5/+13
| | | | | | a partial value. rdar://8782954 llvm-svn: 122078
* Add bits 31-28 to the Thumb2 encoding of TBB/TBH.Jim Grosbach2010-12-171-2/+2
| | | | llvm-svn: 122076
* Handle 2 and 4 byte data blob fixup values for ARM.Jim Grosbach2010-12-171-0/+4
| | | | llvm-svn: 122075
* Stub out explicit MCELFObjectTargetWriter interface.Rafael Espindola2010-12-171-1/+7
| | | | llvm-svn: 122067
* Move createELFObjectWriter to its own header.Rafael Espindola2010-12-171-0/+1
| | | | llvm-svn: 122064
* MC/ARM: Use aggressive symbol folding (important for jump tables, for example).Daniel Dunbar2010-12-171-1/+2
| | | | llvm-svn: 122044
* MC/Target: Remove HasScatteredSymbols target hook variable, which has beenDaniel Dunbar2010-12-171-6/+2
| | | | | | superceded and was effectively dead. llvm-svn: 122024
* Use PairDRegs to implement ConcatVectors. No functionality change.Bob Wilson2010-12-171-7/+1
| | | | llvm-svn: 122017
* Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974Jim Grosbach2010-12-162-3/+12
| | | | llvm-svn: 121990
* MC/Mach-O: Lift some MachObjectWriter arguments into the target specificDaniel Dunbar2010-12-161-4/+9
| | | | | | interface. llvm-svn: 121981
* MC/Mach-O: Stub out explicit MCMachObjectTargetWriter interface.Daniel Dunbar2010-12-161-1/+5
| | | | llvm-svn: 121973
* MC/Mach-O: Move createMachObjectWriter into MCMachObjectWriter.h.Daniel Dunbar2010-12-161-0/+1
| | | | llvm-svn: 121971
* MC: Move target specific fixup info descriptors to TargetAsmBackend instead ofDaniel Dunbar2010-12-162-39/+40
| | | | | | | the MCCodeEmitter, which seems like a better organization. - Also, cleaned up some magic constants while in the area. llvm-svn: 121953
* Delete an extra "Imm5 = ", caught by GCC's -Wsequence-point but not by ClangMatt Beaumont-Gay2010-12-161-1/+1
| | | | | | (see PR4579). llvm-svn: 121939
* Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff forBill Wendling2010-12-163-18/+1
| | | | | | it. I.e., it was always an immediate value. llvm-svn: 121932
* Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRiBill Wendling2010-12-161-0/+2
| | | | | | | | | respectively. It may be a bug that these opcodes are getting this far into machine code generation. llvm-svn: 121931
* Add encodings for Thumb1 Spill and Restore pseudos.Bill Wendling2010-12-161-2/+12
| | | | llvm-svn: 121929
* Thumb1 had two patterns for the same load-from-constant-pool instruction.Jim Grosbach2010-12-154-16/+2
| | | | | | Canonicalize on tLDRpci and remove tLDRcp. llvm-svn: 121920
* Don't handle -arm-long-calls in fast isel for now.Eric Christopher2010-12-152-1/+9
| | | | llvm-svn: 121919
* If we're changing the frame register to a physical register other than SP, weBill Wendling2010-12-152-29/+38
| | | | | | need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively. llvm-svn: 121915
* Whitespace cleanups.Bill Wendling2010-12-151-3/+3
| | | | llvm-svn: 121914
* Add Neon VCVT instructions for f32 <-> f16 conversions.Bob Wilson2010-12-153-1/+22
| | | | | | | Clang is now providing intrinsics for these and so we need to support them in the backend. Radar 8068427. llvm-svn: 121902
* Tweak a few pseudo-inst pattern base classes.Jim Grosbach2010-12-151-4/+4
| | | | llvm-svn: 121878
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