Commit message (Collapse) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Implement a MachineFunctionPass to fix the mul instruction | Rafael Espindola | 2006-09-19 | 4 | -1/+74 |
| | | | | llvm-svn: 30485 | ||||
* | add shifts to addressing mode 1 | Rafael Espindola | 2006-09-13 | 6 | -32/+81 |
| | | | | llvm-svn: 30291 | ||||
* | Reflects MachineConstantPoolEntry changes. | Evan Cheng | 2006-09-12 | 1 | -1/+1 |
| | | | | llvm-svn: 30279 | ||||
* | implement SRL and MUL | Rafael Espindola | 2006-09-11 | 1 | -0/+9 |
| | | | | llvm-svn: 30262 | ||||
* | add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1 | Rafael Espindola | 2006-09-11 | 1 | -6/+3 |
| | | | | llvm-svn: 30261 | ||||
* | partial implementation of the ARM Addressing Mode 1 | Rafael Espindola | 2006-09-11 | 5 | -37/+74 |
| | | | | llvm-svn: 30252 | ||||
* | call AsmPrinter::doInitialization in ARMAsmPrinter::doInitialization | Rafael Espindola | 2006-09-11 | 1 | -0/+1 |
| | | | | llvm-svn: 30246 | ||||
* | Removed unnecessary Mangler creation. | Anton Korobeynikov | 2006-09-10 | 1 | -1/+0 |
| | | | | llvm-svn: 30239 | ||||
* | implement shl and sra | Rafael Espindola | 2006-09-08 | 1 | -0/+12 |
| | | | | llvm-svn: 30191 | ||||
* | add the eor (xor) instruction | Rafael Espindola | 2006-09-08 | 1 | -0/+5 |
| | | | | llvm-svn: 30189 | ||||
* | implement unconditional branches | Rafael Espindola | 2006-09-08 | 1 | -0/+4 |
| | | | | | | fix select.ll llvm-svn: 30186 | ||||
* | 1. Remove condition on delete. | Jim Laskey | 2006-09-07 | 2 | -5/+11 |
| | | | | | | | | 2. Protect and outline createTargetAsmInfo. 3. Misc. kruft. llvm-svn: 30169 | ||||
* | Make target asm info a property of the target machine. | Jim Laskey | 2006-09-07 | 2 | -15/+7 |
| | | | | llvm-svn: 30162 | ||||
* | Break out target asm info into separate files. | Jim Laskey | 2006-09-07 | 2 | -0/+57 |
| | | | | llvm-svn: 30161 | ||||
* | Separate target specific asm properties from the asm printers. | Jim Laskey | 2006-09-06 | 1 | -4/+12 |
| | | | | llvm-svn: 30126 | ||||
* | add the orr instruction | Rafael Espindola | 2006-09-06 | 1 | -0/+4 |
| | | | | llvm-svn: 30125 | ||||
* | Completely eliminate def&use operands. Now a register operand is EITHER a | Chris Lattner | 2006-09-05 | 1 | -2/+2 |
| | | | | | | def operand or a use operand. llvm-svn: 30109 | ||||
* | add support for returning 64bit values | Rafael Espindola | 2006-09-04 | 1 | -0/+9 |
| | | | | llvm-svn: 30103 | ||||
* | Completely rearchitect the interface between targets and the pass manager. | Chris Lattner | 2006-09-04 | 2 | -54/+11 |
| | | | | | | | | | | | | | | | | | | | | | | | | This pass: 1. Splits TargetMachine into TargetMachine (generic targets, can be implemented any way, like the CBE) and LLVMTargetMachine (subclass of TM that is used by things using libcodegen and other support). 2. Instead of having each target fully populate the passmgr for file or JIT output, move all this to common code, and give targets hooks they can implement. 3. Commonalize the target population stuff between file emission and JIT emission. 4. All (native code) codegen stuff now happens in a FunctionPassManager, which paves the way for "fast -O0" stuff in the CFE later, and now LLC could lazily stream .bc files from disk to use less memory. 5. There are now many fewer #includes and the targets don't depend on the scalar xforms or libanalysis anymore (but codegen does). 6. Changing common code generator pass ordering stuff no longer requires touching all targets. 7. The JIT now has the option of "-fast" codegen or normal optimized codegen, which is now orthogonal to the fact that JIT'ing is being done. llvm-svn: 30081 | ||||
* | Simplify target construction. | Chris Lattner | 2006-09-03 | 1 | -2/+1 |
| | | | | llvm-svn: 30070 | ||||
* | add the SETULT condition code | Rafael Espindola | 2006-09-03 | 1 | -0/+1 |
| | | | | llvm-svn: 30067 | ||||
* | add more condition codes | Rafael Espindola | 2006-09-02 | 2 | -2/+30 |
| | | | | llvm-svn: 30056 | ||||
* | Select() no longer require Result operand by reference. | Evan Cheng | 2006-08-26 | 1 | -3/+3 |
| | | | | llvm-svn: 29898 | ||||
* | use @ for comments | Rafael Espindola | 2006-08-25 | 3 | -14/+61 |
| | | | | | | | store LR in an arbitrary stack slot add support for writing varargs functions llvm-svn: 29876 | ||||
* | add the "eq" condition code | Rafael Espindola | 2006-08-24 | 3 | -8/+13 |
| | | | | | | implement a movcond instruction llvm-svn: 29857 | ||||
* | create a generic bcond instruction that has a conditional code argument | Rafael Espindola | 2006-08-24 | 4 | -8/+34 |
| | | | | llvm-svn: 29856 | ||||
* | initial support for branches | Rafael Espindola | 2006-08-24 | 3 | -3/+30 |
| | | | | llvm-svn: 29854 | ||||
* | add a README.txt | Rafael Espindola | 2006-08-22 | 1 | -0/+9 |
| | | | | llvm-svn: 29814 | ||||
* | initial support for select | Rafael Espindola | 2006-08-21 | 3 | -1/+42 |
| | | | | llvm-svn: 29802 | ||||
* | add the and instruction | Rafael Espindola | 2006-08-21 | 1 | -0/+4 |
| | | | | llvm-svn: 29793 | ||||
* | call computeRegisterProperties | Rafael Espindola | 2006-08-20 | 1 | -0/+6 |
| | | | | llvm-svn: 29780 | ||||
* | Constify some methods. Patch provided by Anton Vayvod, thanks! | Chris Lattner | 2006-08-17 | 1 | -2/+2 |
| | | | | llvm-svn: 29756 | ||||
* | add a "load effective address" | Rafael Espindola | 2006-08-17 | 4 | -10/+30 |
| | | | | llvm-svn: 29748 | ||||
* | Declare the callee saved regs | Rafael Espindola | 2006-08-16 | 6 | -14/+60 |
| | | | | | | | Remove the hard coded store and load of the link register Implement ARMFrameInfo llvm-svn: 29727 | ||||
* | select code like | Rafael Espindola | 2006-08-14 | 1 | -1/+34 |
| | | | | | | ldr rx, [ry, #offset] llvm-svn: 29664 | ||||
* | Eliminate use of getNode that takes a vector. | Chris Lattner | 2006-08-11 | 1 | -1/+2 |
| | | | | llvm-svn: 29614 | ||||
* | elimiante use of getNode that takes vector of operands. | Chris Lattner | 2006-08-11 | 1 | -3/+4 |
| | | | | llvm-svn: 29612 | ||||
* | Match tablegen changes. | Evan Cheng | 2006-08-11 | 1 | -3/+4 |
| | | | | llvm-svn: 29604 | ||||
* | CALLSEQ_* produces chain even if that's not needed. | Evan Cheng | 2006-08-11 | 1 | -2/+4 |
| | | | | llvm-svn: 29603 | ||||
* | correctly set LocalAreaOffset of TargetFrameInfo | Rafael Espindola | 2006-08-09 | 2 | -6/+1 |
| | | | | llvm-svn: 29589 | ||||
* | fix the spill code | Rafael Espindola | 2006-08-09 | 2 | -7/+15 |
| | | | | llvm-svn: 29583 | ||||
* | fix the loading of the link register in emitepilogue | Rafael Espindola | 2006-08-09 | 1 | -1/+3 |
| | | | | llvm-svn: 29580 | ||||
* | change the addressing mode of the str instruction to reg+imm | Rafael Espindola | 2006-08-08 | 4 | -7/+13 |
| | | | | llvm-svn: 29571 | ||||
* | initial support for variable number of arguments | Rafael Espindola | 2006-08-08 | 2 | -12/+37 |
| | | | | llvm-svn: 29567 | ||||
* | Match tablegen isel changes. | Evan Cheng | 2006-08-07 | 1 | -3/+1 |
| | | | | llvm-svn: 29549 | ||||
* | use a 'register pressure reducing' scheduler | Rafael Espindola | 2006-08-04 | 1 | -0/+2 |
| | | | | | | make sure only one move is used in a hello world llvm-svn: 29520 | ||||
* | Bug fix: always generate a RET_FLAG in LowerRET | Rafael Espindola | 2006-08-03 | 1 | -1/+1 |
| | | | | | | fixes ret_null.ll and call.ll llvm-svn: 29519 | ||||
* | add and use ARMISD::RET_FLAG | Rafael Espindola | 2006-08-03 | 2 | -9/+10 |
| | | | | llvm-svn: 29499 | ||||
* | start comments with # | Rafael Espindola | 2006-08-01 | 2 | -7/+21 |
| | | | | | | | | move the constant pool to .text correctly print loads of labels mark R0, R1, R2 and R3 as caller save llvm-svn: 29451 | ||||
* | implement LowerConstantPool and LowerGlobalAddress | Rafael Espindola | 2006-08-01 | 2 | -3/+26 |
| | | | | llvm-svn: 29433 |