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* We are not using DBG_STOPPOINT anymore.Devang Patel2009-11-211-1/+0
| | | | llvm-svn: 89536
* Remat VLDRD from constpool. Clean up some instruction property specifications.Evan Cheng2009-11-204-9/+10
| | | | llvm-svn: 89478
* The verify() call of CPEIsInRange() isn't right for the assertion check ofJim Grosbach2009-11-201-2/+5
| | | | | | | | | | constant pool ranges, as CPEIsInRange() makes conservative assumptions about the potential alignment changes from branch adjustments. The verification, on the other hand, runs after those branch adjustments are made, so the effects on alignment are known and already taken into account. The sanity check in verify should check the range directly instead. llvm-svn: 89473
* Remove verifySizes() since it's not adding much value.Jim Grosbach2009-11-201-36/+0
| | | | llvm-svn: 89443
* Also CSE non-pic load from constant pools.Evan Cheng2009-11-201-1/+4
| | | | llvm-svn: 89440
* Fix codegen of conditional move of immediates. We were not making use of the ↵Evan Cheng2009-11-201-65/+127
| | | | | | immediate forms of cmov instructions at all. llvm-svn: 89423
* Update comment to reflect instruction.Eric Christopher2009-11-201-1/+1
| | | | llvm-svn: 89414
* When placing constant islands and adjusting for alignment padding, inlineJim Grosbach2009-11-191-7/+66
| | | | | | | | | | | assembly can confuse things utterly, as it's assumed that instructions in inline assembly are 4 bytes wide. For Thumb mode, that's often not true, so the calculations for when alignment padding will be present get thrown off, ultimately leading to out of range constant pool entry references. Making more conservative assumptions that padding may be necessary when inline asm is present avoids this situation. llvm-svn: 89403
* Refactor cmov selection code out to a separate function. No functionality ↵Evan Cheng2009-11-191-116/+122
| | | | | | change. llvm-svn: 89396
* Added NLdStLN which is similar to NLdSt with the exception that op7_4 is notJohnny Chen2009-11-192-76/+169
| | | | | | | | fully specified at this level. Subclasses of NLdStLN can specify selective bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside ARMInstrNEON.td. llvm-svn: 89377
* fix typoJim Grosbach2009-11-191-1/+1
| | | | llvm-svn: 89369
* 80 col violation.Evan Cheng2009-11-191-1/+2
| | | | llvm-svn: 89337
* More consistent thumb1 asm printing.Evan Cheng2009-11-194-11/+27
| | | | llvm-svn: 89328
* Shrink ldr / str [sp, imm0-1024] to 16-bit instructions.Evan Cheng2009-11-191-8/+26
| | | | llvm-svn: 89326
* Eliminate more * 4 in Thumb1 asm printing for consistency sake.Evan Cheng2009-11-191-4/+4
| | | | llvm-svn: 89325
* Add ARMv6 itineraries.David Goodwin2009-11-183-13/+201
| | | | llvm-svn: 89218
* Fix a few places that were missed when we converted to unified syntax.Bob Wilson2009-11-181-2/+2
| | | | llvm-svn: 89214
* Add a target hook to allow changing the tail duplication limit based on theBob Wilson2009-11-184-0/+20
| | | | | | | | | contents of the block to be duplicated. Use this for ARM Cortex A8/9 to be more aggressive tail duplicating indirect branches, since it makes it much more likely that they will be predicted in the branch target buffer. Testcase coming soon. llvm-svn: 89187
* Enable arm jumpt table adjustment.Jim Grosbach2009-11-171-1/+1
| | | | llvm-svn: 89143
* Both Darwin as and GNU as violate ARM docs wrt printing of addrmode6Anton Korobeynikov2009-11-171-5/+2
| | | | | | alignment imm (in the same way). Fix asmprinting for non-darwin platforms. llvm-svn: 89137
* Set Inst{15-12} (Rd/Rt) to 0b1111 (PC) for BR_JTadd, BR_JTr, and BR_JTm toJohnny Chen2009-11-171-0/+3
| | | | | | distinguish between them and the more generic instructions (add, mov, and ldr). llvm-svn: 89108
* When moving a block for table jumps, make sure the prior block terminatorJim Grosbach2009-11-171-7/+9
| | | | | | | is analyzable so it can be updated. If it's not, be safe and don't move the block. llvm-svn: 89022
* Set Rm bits of BX_RET to 0b1110 (R14); and set condition code bits of BRIND toJohnny Chen2009-11-161-0/+2
| | | | | | | 0b1110 (ALways). This is so that the disassembler decoder can distinguish among BX_RET, BRIND, and BXr9. llvm-svn: 89000
* Make the pass class name more explicit.Jim Grosbach2009-11-161-4/+6
| | | | llvm-svn: 88964
* make pass name a bit more clearJim Grosbach2009-11-161-1/+1
| | | | llvm-svn: 88961
* Simplify thumb2 jump table adjustments. Remove unnecessary calculation andJim Grosbach2009-11-161-58/+14
| | | | | | usage of block sizes and offsets. llvm-svn: 88935
* clarify commentJim Grosbach2009-11-161-2/+2
| | | | llvm-svn: 88933
* back off for a bit. tracking down weirdnessJim Grosbach2009-11-161-1/+1
| | | | llvm-svn: 88919
* Analyze has to be before checking the condition, obviously. Properly ↵Jim Grosbach2009-11-161-6/+8
| | | | | | construct an iterator for prior. llvm-svn: 88917
* Detect need for autoalignment of the stack earlier to catch spills moreJim Grosbach2009-11-154-2/+51
| | | | | | | conservatively. eliminateFrameIndex() machinery adjust to handle addr mode 6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling llvm-svn: 88874
* set the def of the VLD1q64 properlyJim Grosbach2009-11-151-2/+1
| | | | llvm-svn: 88873
* cleanup.Jim Grosbach2009-11-141-3/+1
| | | | llvm-svn: 88812
* Cleanup flow, and only update the jump table we're analyzing when replacing ↵Jim Grosbach2009-11-141-9/+11
| | | | | | a destination MBB. llvm-svn: 88805
* - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.Evan Cheng2009-11-144-6/+15
| | | | | | | | - If destination is a physical register and it has a subreg index, use the sub-register instead. This fixes PR5423. llvm-svn: 88745
* When expanding t2STRDi8 r, r to two stores, add kill markers correctly.Evan Cheng2009-11-141-0/+7
| | | | llvm-svn: 88734
* Move DebugInfo checks into EmitComments and remove them fromDavid Greene2009-11-131-1/+1
| | | | | | | | target-specific AsmPrinters. Not all comments need DebugInfo. Re-enable the line numbers comment test. llvm-svn: 88697
* Allow target to specify regclass for which antideps will only be broken ↵David Goodwin2009-11-132-4/+4
| | | | | | along the critical path. llvm-svn: 88682
* Block renumberingJim Grosbach2009-11-131-3/+1
| | | | llvm-svn: 87056
* use lower case for readabilityJim Grosbach2009-11-131-1/+1
| | | | llvm-svn: 87054
* Make the MachineFunction argument of getFrameRegister const.David Greene2009-11-121-1/+1
| | | | | | This also fixes a build error. llvm-svn: 87027
* Add a bool flag to StackObjects telling whether they reference spillDavid Greene2009-11-122-6/+11
| | | | | | | | | | | | | slots. The AsmPrinter will use this information to determine whether to print a spill/reload comment. Remove default argument values. It's too easy to pass a wrong argument value when multiple arguments have default values. Make everything explicit to trap bugs early. Update all targets to adhere to the new interfaces.. llvm-svn: 87022
* Update TB[BH] layout optimization. Add support for moving the target blockJim Grosbach2009-11-121-33/+115
| | | | | | | to directly follow the jump table. Move the layout changes to prior to any constant island handling. llvm-svn: 86999
* Use table to separate opcode from operands.Evan Cheng2009-11-121-2/+2
| | | | llvm-svn: 86965
* isLegalICmpImmediate should take a signed integer; code clean up.Evan Cheng2009-11-122-32/+30
| | | | llvm-svn: 86964
* Revert 86857. It's causing consumer-typeset to fail, and there's a better ↵Jim Grosbach2009-11-121-7/+4
| | | | | | way to do it forthcoming anyway. llvm-svn: 86945
* Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be ↵Evan Cheng2009-11-112-0/+18
| | | | | | folded into target icmp instructions. llvm-svn: 86858
* Do jump table adjustment before constant island allocationJim Grosbach2009-11-111-4/+7
| | | | llvm-svn: 86857
* The TBB and TBH instructions for Thumb2 are really handy for jump tables, butJim Grosbach2009-11-111-3/+96
| | | | | | | | | | | can only branch forward. To best take advantage of them, we'd like to adjust the basic blocks around a bit when reasonable. This patch puts basics in place to do that, with a super-simple algorithm for backwards jump table targets that creates a new branch after the jump table which branches backwards. Real heuristics for reordering blocks or other modifications rather than inserting branches will follow. llvm-svn: 86791
* Change Thumb1 address mode printing, instead ofEvan Cheng2009-11-101-5/+2
| | | | | | | | | | [r0, #2 * 4] Now [r0, #8] This makes Thumb2 assembly more uniform and frankly the scale doesn't add much. llvm-svn: 86707
* Add a comment.Evan Cheng2009-11-101-0/+2
| | | | llvm-svn: 86706
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