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* Correct ARM NOP encodingDavid Sehr2012-12-051-1/+1
| | | | | | | | | | The encoding of NOP in ARMAsmBackend.cpp is missing a trailing zero, which causes the emission of a coprocessor instruction rather than "mov r0, r0" as indicated in the comment. The test also checks for the wrong encoding. http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121203/157919.html llvm-svn: 169420
* Added a option to the disassembler to print immediates as hex.Kevin Enderby2012-12-051-7/+7
| | | | | | | | | | | | | | | | | | | | This is for the lldb team so most of but not all of the values are to be printed as hex with this option. Some small values like the scale in an X86 address were requested to printed in decimal without the leading 0x. There may be some tweaks need to places that may still be in decimal that they want in hex. Specially for arm. I made my best guess. Any tweaks from here should be simple. I also did the best I know now with help from the C++ gurus creating the cleanest formatImm() utility function and containing the changes. But if someone has a better idea to make something cleaner I'm all ears and game for changing the implementation. rdar://8109283 llvm-svn: 169393
* Appease GCC's -Wparentheses.Matt Beaumont-Gay2012-12-041-2/+2
| | | | | | (TIL that Clang's -Wparentheses ignores 'x || y && "foo"' on purpose. Neat.) llvm-svn: 169337
* ARM custom lower ctpop for vector types. Patch by Pete Couperus.Evan Cheng2012-12-041-0/+117
| | | | llvm-svn: 169325
* Make NaCl naming consistent. The triple OSType is called NaCl and is representedEli Bendersky2012-12-041-1/+1
| | | | | | | | | textually as NativeClient. Also added a link to the native client project for readers unfamiliar with it. A Clang patch will follow shortly. llvm-svn: 169291
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-046-18/+18
| | | | | | | | | | missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
* Remove the old TRI::ResolveRegAllocHint() and getRawAllocationOrder() hooks.Jakob Stoklund Olesen2012-12-042-270/+0
| | | | | | | These functions have been replaced by TRI::getRegAllocationHints() which provides the same capabilities. llvm-svn: 169192
* Implement ARMBaseRegisterInfo::getRegAllocationHints().Jakob Stoklund Olesen2012-12-032-0/+65
| | | | | | | This provides the same functionality as getRawAllocationOrder() for the even/odd hints, but without the many constant register arrays. llvm-svn: 169169
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-0334-152/+149
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Codegen failure for vmull with small vectorsSebastian Pop2012-11-301-13/+74
| | | | | | | | | | | | | | | | | | | | | | | | | Codegen was failing with an assertion because of unexpected vector operands when legalizing the selection DAG for a MUL instruction. The asserting code was legalizing multiplies for vectors of size 128 bits. It uses a custom lowering to try and detect cases where it can use a VMULL instruction instead of a VMOVL + VMUL. The code was looking for input operands to the MUL that had been sign or zero extended. If it found the extended operands it would drop the sign/zero extension and use the original vector size as input to a VMULL instruction. The code assumed that the original input vector was 64 bits so that after dropping the extension it would fit directly into a D register and could be used as an operand of a VMULL instruction. The input code that trigger the failure used a vector of <4 x i8> that was sign extended to <4 x i32>. It was not safe to drop the sign extension in this case because the original vector is only 32 bits wide. The fix is to insert a sign extension for the vector to reach the required 64 bit size. In this particular example, the vector would need to be sign extented to a <4 x i16>. llvm-svn: 169024
* Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInstKevin Enderby2012-11-291-1/+7
| | | | | | which would then cause an assert when printed. rdar://11437956 llvm-svn: 168960
* Add cortex-a5 subtarget to the supported ARM architecturesQuentin Colombet2012-11-292-1/+12
| | | | llvm-svn: 168933
* Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend.Silviu Baranga2012-11-294-12/+102
| | | | llvm-svn: 168886
* ARM: Implement CanLowerReturn so large vectors get expanded into sret.Benjamin Kramer2012-11-282-0/+17
| | | | | | Fixes 14337. llvm-svn: 168809
* Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen2012-11-282-7/+7
| | | | | | This class has been merged into its super-class TargetInstrInfo. llvm-svn: 168760
* [arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier2012-11-271-9/+7
| | | | | | | | | classes. The vast majority of the remaining issues are due to uses of invalid registers, which are defined by getRegForValue(). Those will be a little more challenging to cleanup. rdar://12719844 llvm-svn: 168735
* [arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier2012-11-271-2/+4
| | | | | | | classes. rdar://12719844 llvm-svn: 168733
* [arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier2012-11-271-5/+6
| | | | | | | classes. Also a bit of cleanup. rdar://12719844 llvm-svn: 168728
* [arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier2012-11-271-4/+10
| | | | | | | | classes. The associated test case still doesn't pass, but it does have far fewer issues. rdar://12719844 llvm-svn: 168657
* Decouple MCInstBuilder from the streamer per Eli's request.Benjamin Kramer2012-11-261-114/+78
| | | | llvm-svn: 168597
* Add MCInstBuilder, a utility class to simplify MCInst creation similar to ↵Benjamin Kramer2012-11-261-376/+298
| | | | | | | | MachineInstrBuilder. Simplify some repetitive code with it. No functionality change. llvm-svn: 168587
* ARM: Share applyFixup between ELF and Darwin.Benjamin Kramer2012-11-241-63/+46
| | | | | | The implementations already diverged a bit, merge them back together. llvm-svn: 168542
* Mark FP_EXTEND form v2f32 to v2f64 as "expand" for ARM NEON. Patch by Pete ↵Eli Friedman2012-11-171-0/+1
| | | | | | Couperus. llvm-svn: 168240
* Rename methods like PairSRegs() to createSRegpairNode() to meet our codingWeiming Zhao2012-11-171-40/+34
| | | | | | style requirement. llvm-svn: 168229
* Remove hard coded registers in ARM ldrexd and strexd instructionsWeiming Zhao2012-11-166-62/+185
| | | | | | | | | This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
* Make sure FABS on v2f32 and v4f32 is legal on ARM NEONAnton Korobeynikov2012-11-162-7/+9
| | | | | | This fixes PR14359 llvm-svn: 168200
* Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missingEli Friedman2012-11-151-0/+2
| | | | | | | | case to vector legalization so this actually works. Patch by Pete Couperus. Fixes PR12540. llvm-svn: 168107
* Use empty parens for empty function parameter list instead of '(void)'.Dmitri Gribenko2012-11-153-3/+3
| | | | llvm-svn: 168049
* Revert changing FNEG of v4f32 to Expand. It's legal.Craig Topper2012-11-151-1/+0
| | | | llvm-svn: 168030
* Make FNEG and FABS of v4f32 Expand.Craig Topper2012-11-151-0/+2
| | | | llvm-svn: 168029
* Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics.Craig Topper2012-11-151-0/+4
| | | | llvm-svn: 168025
* The code pattern "imm0_255_neg" is used for checking if an immediate value ↵Nadav Rotem2012-11-141-6/+7
| | | | | | | | | | | is a small negative number. This patch changes the definition of negative from -0..-255 to -1..-255. I am changing this because of a bug that we had in some of the patterns that assumed that "subs" of zero does not set the carry flag. rdar://12028498 llvm-svn: 167963
* Use TARGET2 relocation for TType references on ARM.Anton Korobeynikov2012-11-142-1/+19
| | | | | | | | Do some cleanup of the code while here. Inspired by patch by Logan Chien! llvm-svn: 167904
* misched: Target-independent support for load/store clustering.Andrew Trick2012-11-121-0/+6
| | | | | | | | | | This infrastructure is generally useful for any target that wants to strongly prefer two instructions to be adjacent after scheduling. A following checkin will add target-specific hooks with unit tests. Then this feature will be enabled by default with misched. llvm-svn: 167742
* Disable the Thumb no-return call optimization:Evan Cheng2012-11-103-47/+2
| | | | | | | | | | | | mov lr, pc b.w _foo The "mov" instruction doesn't set bit zero to one, it's putting incorrect value in lr. It messes up backtraces. rdar://12663632 llvm-svn: 167657
* Add ARM TARGET2 relocation. The testcase will follow with actualy use-case.Anton Korobeynikov2012-11-091-0/+3
| | | | | | Based on the patch by Logan Chien! llvm-svn: 167633
* Revert r167620; this can be implemented using an existing CL option.Chad Rosier2012-11-092-10/+5
| | | | llvm-svn: 167622
* Add support for -mstrict-align compiler option for ARM targets.Chad Rosier2012-11-092-5/+10
| | | | | | rdar://12340498 llvm-svn: 167620
* Recommit modified r167540.Amara Emerson2012-11-081-4/+19
| | | | | | | Improve ARM build attribute emission for architectures types. This also changes the default architecture emitted for a generic CPU to "v7". llvm-svn: 167574
* Revert r167540 until regression tests are updated.Amara Emerson2012-11-071-21/+4
| | | | llvm-svn: 167545
* Improve ARM build attribute emission for architectures types.Amara Emerson2012-11-071-4/+21
| | | | | | This also changes the default architecture emitted for a generic CPU to "v7". llvm-svn: 167540
* [arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier2012-11-071-1/+4
| | | | | | | classes. For my test case the number of errors drop from 356 to 21. Part of rdar://12594152 llvm-svn: 167508
* Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering allChad Rosier2012-11-067-28/+23
| | | | | | | | | | | | registers. Previously, the register we being marked as implicitly defined, but not killed. In some cases this would cause the register scavenger to spill a dead register. Also, use an empty register mask to simplify the logic and to reduce the memory footprint. rdar://12592448 llvm-svn: 167499
* Vext Lowering was missing opportunitiesQuentin Colombet2012-11-021-4/+40
| | | | llvm-svn: 167318
* Revert the series of commits starting with r166578 which introduced theChandler Carruth2012-11-011-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | getIntPtrType support for multiple address spaces via a pointer type, and also introduced a crasher bug in the constant folder reported in PR14233. These commits also contained several problems that should really be addressed before they are re-committed. I have avoided reverting various cleanups to the DataLayout APIs that are reasonable to have moving forward in order to reduce the amount of churn, and minimize the number of commits that were reverted. I've also manually updated merge conflicts and manually arranged for the getIntPtrType function to stay in DataLayout and to be defined in a plausible way after this revert. Thanks to Duncan for working through this exact strategy with me, and Nick Lewycky for tracking down the really annoying crasher this triggered. (Test case to follow in its own commit.) After discussing with Duncan extensively, and based on a note from Micah, I'm going to continue to back out some more of the more problematic patches in this series in order to ensure we go into the LLVM 3.2 branch with a reasonable story here. I'll send a note to llvmdev explaining what's going on and why. Summary of reverted revisions: r166634: Fix a compiler warning with an unused variable. r166607: Add some cleanup to the DataLayout changes requested by Chandler. r166596: Revert "Back out r166591, not sure why this made it through since I cancelled the command. Bleh, sorry about this! r166591: Delete a directory that wasn't supposed to be checked in yet. r166578: Add in support for getIntPtrType to get the pointer type based on the address space. llvm-svn: 167221
* Change ForceSizeOpt attribute into MinSize attributeQuentin Colombet2012-10-301-4/+4
| | | | llvm-svn: 167020
* ARM: Better disassembly for pc-relative LDR.Jim Grosbach2012-10-304-4/+6
| | | | | | | | | When the operand is a plain immediate rather than a label, print it as [pc, #imm] like we do for the Thumb2 wide encoding variant. rdar://12154503 llvm-svn: 166991
* Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch targetKevin Enderby2012-10-292-11/+23
| | | | | | | is 24 bits not 20 and the decoding needed to correctly handle converting the J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. llvm-svn: 166982
* Remove TargetELFWriterInfo.Rafael Espindola2012-10-285-149/+0
| | | | | | All the credit goes to Jan Voung for noticing it was dead! llvm-svn: 166902
* [code size][ARM] Emit regular call instructions instead of the move, branch ↵Quentin Colombet2012-10-271-2/+8
| | | | | | sequence llvm-svn: 166854
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