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* even more simplifications. ARM MCInstLowering is now justChris Lattner2010-11-144-60/+19
| | | | | | | a single function instead of a class. It doesn't need the complexity that X86 does. llvm-svn: 119070
* more shrinkificationChris Lattner2010-11-142-10/+1
| | | | llvm-svn: 119068
* more simplifications.Chris Lattner2010-11-142-92/+18
| | | | llvm-svn: 119067
* simplify and tidy upChris Lattner2010-11-143-41/+16
| | | | llvm-svn: 119066
* stub out a powerpc MCInstPrinter implementation.Chris Lattner2010-11-141-1/+1
| | | | llvm-svn: 119059
* Second attempt at providing correct encodings for Thumb2 binary operators.Owen Anderson2010-11-141-51/+105
| | | | llvm-svn: 119029
* Comment out the defms until they're activated.Bill Wendling2010-11-133-3/+7
| | | | llvm-svn: 119000
* Add uses of the *_ldst_multi multiclasses. These aren't used yet.Bill Wendling2010-11-134-0/+48
| | | | llvm-svn: 118999
* Convert the modes to lower case.Bill Wendling2010-11-134-22/+22
| | | | llvm-svn: 118998
* Minor cleanups:Bill Wendling2010-11-132-11/+14
| | | | | | | - Get the opcode once. - Add a ParserMatchClass to reglist. llvm-svn: 118997
* Add *_ldst_mult multiclasses to the ARM back-end. These will be used in theBill Wendling2010-11-135-0/+229
| | | | | | | future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
* MC: Simplify Mach-O and ELF object writer implementations.Daniel Dunbar2010-11-131-8/+7
| | | | | | - What was I thinking????? llvm-svn: 118992
* Conditional moves are slightly more expensive than moves.Evan Cheng2010-11-136-10/+11
| | | | llvm-svn: 118985
* Add conditional move of large immediate.Evan Cheng2010-11-134-18/+47
| | | | llvm-svn: 118968
* Swap multiclass operand order for consistency with other patterns.Jim Grosbach2010-11-131-3/+3
| | | | llvm-svn: 118965
* Continue ARM indexed load refactoring. Multiclass for LDR{B} pre/post indexedJim Grosbach2010-11-131-18/+12
| | | | | | instructions. llvm-svn: 118963
* More ARM load/store indexed refactoring. Also fix an incorrect IndexModeJim Grosbach2010-11-132-75/+54
| | | | | | flag for the LDRT/STRT family instructions as a side effect. llvm-svn: 118955
* Fix an obvious typo which inverted an immediate.Evan Cheng2010-11-131-1/+1
| | | | llvm-svn: 118951
* Temporarily revert this.Eric Christopher2010-11-121-5/+4
| | | | llvm-svn: 118946
* For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled ↵Evan Cheng2010-11-123-15/+11
| | | | | | with movi + orr. llvm-svn: 118945
* Revert r118939 while I work out why it broke some buildbots.Owen Anderson2010-11-121-65/+52
| | | | llvm-svn: 118942
* Attemt to provide correct encodings for Thumb2 binary operators.Owen Anderson2010-11-121-52/+65
| | | | llvm-svn: 118939
* Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either ↵Evan Cheng2010-11-125-72/+34
| | | | | | movi+orr or movw+movt depending on the subtarget. llvm-svn: 118938
* Make this happen for ARM like x86. Don't entirely bail out whenEric Christopher2010-11-121-4/+5
| | | | | | | an address is in a different block, get it into a register and go from there. llvm-svn: 118936
* Add conditional mvn instructions.Evan Cheng2010-11-123-10/+67
| | | | llvm-svn: 118935
* Zap a copy/paste-o bit of dead code.Jim Grosbach2010-11-121-2/+0
| | | | llvm-svn: 118926
* Refactor to parameterize some ARM load/store encoding patterns. PreparatoryJim Grosbach2010-11-122-86/+24
| | | | | | | to splitting the load/store pre/post indexed instructions into [r, r] and [r, imm] forms. llvm-svn: 118925
* First stab at providing correct Thumb2 encodings, start with adc.Owen Anderson2010-11-123-19/+122
| | | | llvm-svn: 118924
* Add some missing isel predicates on def : pat patterns to avoid generating ↵Evan Cheng2010-11-123-64/+54
| | | | | | VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next. llvm-svn: 118922
* Kill more unused stuff.Jim Grosbach2010-11-121-43/+0
| | | | llvm-svn: 118921
* Remove unused class.Jim Grosbach2010-11-121-8/+0
| | | | llvm-svn: 118919
* Fill in the default predication bits for ARM unconditional branch.Jim Grosbach2010-11-121-0/+1
| | | | llvm-svn: 118907
* Encoding for ARM LDRSB instructions.Jim Grosbach2010-11-121-7/+12
| | | | llvm-svn: 118905
* Fix up a few more spots of addrmode2 (or not) changes that wereEric Christopher2010-11-121-6/+12
| | | | | | | | missed. Update some comments accordingly. Fixes rdar://8652289 llvm-svn: 118888
* Start of support for binary emit of 16-it Thumb instructions.Jim Grosbach2010-11-112-7/+18
| | | | llvm-svn: 118859
* Fill out support for Thumb2 encodings of NEON instructions.Owen Anderson2010-11-113-0/+21
| | | | llvm-svn: 118854
* Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].Owen Anderson2010-11-113-1/+22
| | | | llvm-svn: 118843
* Revert the accidental commit I made reverting the previous commit.Eric Christopher2010-11-111-6/+7
| | | | llvm-svn: 118835
* ARM fixup encoding for direct call instructions (BL).Jim Grosbach2010-11-111-8/+22
| | | | llvm-svn: 118829
* Revert this temporarily.Eric Christopher2010-11-115-104/+31
| | | | llvm-svn: 118827
* Change the prologue and epilogue to use push/pop for the low ARM registers.Eric Christopher2010-11-114-25/+97
| | | | llvm-svn: 118823
* Add support for Thumb2 encodings of NEON data processing instructions, using ↵Owen Anderson2010-11-113-0/+26
| | | | | | | | the new PostEncoderMethod infrastructure. More tests to come. llvm-svn: 118819
* Encoding of destination fixup for ARM branch and conditional branchJim Grosbach2010-11-115-13/+57
| | | | | | instructions. llvm-svn: 118801
* Encoding for ARM LDRSH_POST.Jim Grosbach2010-11-114-7/+39
| | | | llvm-svn: 118794
* Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.Jim Grosbach2010-11-112-39/+49
| | | | llvm-svn: 118767
* Fix encoding of Ra register for ARM smla* instructions.Jim Grosbach2010-11-111-6/+6
| | | | llvm-svn: 118761
* ARM STRH encoding information.Jim Grosbach2010-11-114-11/+44
| | | | llvm-svn: 118757
* Move LDM predicate operand encoding into base clase. Add STM missing STMJim Grosbach2010-11-102-10/+18
| | | | | | encoding bits. llvm-svn: 118738
* ARM LDM encoding for the mode (ia, ib, da, db) operand.Jim Grosbach2010-11-104-1/+19
| | | | llvm-svn: 118736
* Fix ARM encoding of non-return LDM instructions.Jim Grosbach2010-11-102-4/+11
| | | | llvm-svn: 118732
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