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* ARM: cleanup formattingSaleem Abdulrasool2015-09-201-2/+2
| | | | | | clang-format a line which was poorly formatted. NFC. llvm-svn: 248110
* NFC: Fix indentation and add braces to clarify nested of else-statement.Bob Wilson2015-09-191-2/+3
| | | | llvm-svn: 248086
* Limit the range of processors supported by ARM fast isel to v6 orEric Christopher2015-09-181-0/+4
| | | | | | | | later as that's all that is tested right now. Fixes PR24858. llvm-svn: 248027
* Scaling up values in ARMBaseInstrInfo::isProfitableToIfCvt() before they are ↵Cong Hou2015-09-181-10/+17
| | | | | | | | | | scaled by a probability to avoid precision issue. In ARMBaseInstrInfo::isProfitableToIfCvt(), there is a simple cost model in which the number of cycles is scaled by a probability to estimate the cost. However, when the number of cycles is small (which is usually the case), there is a precision issue after the computation. To avoid this issue, this patch scales those cycles by 1024 (chosen to make the multiplication a litter faster) before they are scaled by the probability. Other variables are also scaled up for the final comparison. Differential Revision: http://reviews.llvm.org/D12742 llvm-svn: 248018
* constify the Function parameter to the TTI creation callback andEric Christopher2015-09-162-3/+4
| | | | | | propagate to all callers/users/etc. llvm-svn: 247864
* propagate fast-math-flags on DAG nodesSanjay Patel2015-09-161-0/+5
| | | | | | | | | | | | | | | | | | | After D10403, we had FMF in the DAG but disabled by default. Nick reported no crashing errors after some stress testing, so I enabled them at r243687. However, Escha soon notified us of a bug not covered by any in-tree regression tests: if we don't propagate the flags, we may fail to CSE DAG nodes because differing FMF causes them to not match. There is one test case in this patch to prove that point. This patch hopes to fix or leave a 'TODO' for all of the in-tree places where we create nodes that are FMF-capable. I did this by putting an assert in SelectionDAG.getNode() to find any FMF-capable node that was being created without FMF ( D11807 ). I then ran all regression tests and test-suite and confirmed that everything passes. This patch exposes remaining work to get DAG FMF to be fully functional: (1) add the flags to non-binary nodes such as FCMP, FMA and FNEG; (2) add the flags to intrinsics; (3) use the flags as conditions for transforms rather than the current global settings. Differential Revision: http://reviews.llvm.org/D12095 llvm-svn: 247815
* [ARM] Register ARMPreAllocLoadStoreOpt pass with LLVM pass manager.Chad Rosier2015-09-161-2/+14
| | | | llvm-svn: 247791
* Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and ↵Daniel Sanders2015-09-1513-86/+80
| | | | | | | | related. NFC. Eric has replied and has demanded the patch be reverted. llvm-svn: 247702
* Re-commit r247683: Replace Triple with a new TargetTuple in MCTargetDesc/* ↵Daniel Sanders2015-09-1513-80/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | and related. NFC. Summary: This is the first patch in the series to migrate Triple's (which are ambiguous) to TargetTuple's (which aren't). For the moment, TargetTuple simply passes all requests to the Triple object it holds. Once it has replaced Triple, it will start to implement the interface in a more suitable way. This change makes some changes to the public C++ API. In particular, InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer() now take TargetTuples instead of Triples. The other public C++ API's have been left as-is for the moment to reduce patch size. This commit also contains a trivial patch to clang to account for the C++ API change. Thanks go to Pavel Labath for fixing LLDB for me. Reviewers: rengolin Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10969 llvm-svn: 247692
* Revert r247684 - Replace Triple with a new TargetTuple ...Daniel Sanders2015-09-1513-86/+80
| | | | | | LLDB needs to be updated in the same commit. llvm-svn: 247686
* Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.Daniel Sanders2015-09-1513-80/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is the first patch in the series to migrate Triple's (which are ambiguous) to TargetTuple's (which aren't). For the moment, TargetTuple simply passes all requests to the Triple object it holds. Once it has replaced Triple, it will start to implement the interface in a more suitable way. This change makes some changes to the public C++ API. In particular, InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer() now take TargetTuples instead of Triples. The other public C++ API's have been left as-is for the moment to reduce patch size. This commit also contains a trivial patch to clang to account for the C++ API change. Reviewers: rengolin Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10969 llvm-svn: 247683
* Fix namespace indentation and missing blank lines before 'public:' in ↵Daniel Sanders2015-09-151-28/+31
| | | | | | | | | | *MCAsmInfo.h. NFC. This is to reduce noise in a following commit. Also fixes a couple missing spaces before the reference operator. llvm-svn: 247679
* [ARM] Extract shifts out of multiply-by-constantJohn Brawn2015-09-141-19/+111
| | | | | | | | | | | | | | | Turning (op x (mul y k)) into (op x (lsl (mul y k>>n) n)) is beneficial when we can do the lsl as a shifted operand and the resulting multiply constant is simpler to generate. Do this by doing the transformation when trying to select a shifted operand, as that ensures that it actually turns out better (the alternative would be to do it in PreprocessISelDAG, but we don't know for sure there if extracting the shift would allow a shifted operand to be used). Differential Revision: http://reviews.llvm.org/D12196 llvm-svn: 247569
* [CodeGen] Refactor TLI/AtomicExpand interface to make LLSC explicit.Ahmed Bougacha2015-09-112-7/+13
| | | | | | | | | | | | | | | We used to have this magic "hasLoadLinkedStoreConditional()" callback, which really meant two things: - expand cmpxchg (to ll/sc). - expand atomic loads using ll/sc (rather than cmpxchg). Remove it, and, instead, introduce explicit callbacks: - bool shouldExpandAtomicCmpXchgInIR(inst) - AtomicExpansionKind shouldExpandAtomicLoadInIR(inst) Differential Revision: http://reviews.llvm.org/D12557 llvm-svn: 247429
* [CodeGen] Rename AtomicRMWExpansionKind to AtomicExpansionKind.Ahmed Bougacha2015-09-112-4/+4
| | | | | | This lets us generalize its usage to the other atomic instructions. llvm-svn: 247428
* Pass BranchProbability/BlockMass by value instead of const& as they are ↵Cong Hou2015-09-102-5/+5
| | | | | | small. NFC. llvm-svn: 247357
* [ARM] Do not use vtrn for vectorshuffle if the order is reversedJames Molloy2015-09-101-4/+13
| | | | | | | | The tests in isVTRNMask and isVTRN_v_undef_Mask should also check that the elements of the upper and lower half of the vectorshuffle occur in the correct order when both halves are used. Without this test the code assumes that it is correct to use vector transpose (vtrn) for the masks <1, 1, 0, 0> and <1, 3, 0, 2>, among others, but the transpose actually incorrectly generates shuffles for <0, 0, 1, 1> and <0, 2, 1, 3> in this case. Patch by Jeroen Ketema! llvm-svn: 247254
* [ADT] Switch a bunch of places in LLVM that were doing single-characterChandler Carruth2015-09-101-2/+2
| | | | | | | splits to actually use the single character split routine which does less work, and in a debug build is *substantially* faster. llvm-svn: 247245
* Save LaneMask with livein registersMatthias Braun2015-09-091-1/+1
| | | | | | | | | | | | | | | | | With subregister liveness enabled we can detect the case where only parts of a register are live in, this is expressed as a 32bit lanemask. The current code only keeps registers in the live-in list and therefore enumerated all subregisters affected by the lanemask. This turned out to be too conservative as the subregister may also cover additional parts of the lanemask which are not live. Expressing a given lanemask by enumerating a minimum set of subregisters is computationally expensive so the best solution is to simply change the live-in list to store the lanemasks as well. This will reduce memory usage for targets using subregister liveness and slightly increase it for other targets Differential Revision: http://reviews.llvm.org/D12442 llvm-svn: 247171
* [ARM] Get rid of SelectT2ShifterOperandReg, NFCJohn Brawn2015-09-072-26/+2
| | | | | | | | | SelectT2ShifterOperandReg has identical behaviour to SelectImmShifterOperand, so get rid of it and use SelectImmShifterOperand instead. Differential Revision: http://reviews.llvm.org/D12195 llvm-svn: 246962
* [ARM] Don't abort on variable-idx extractelt in ReconstructShuffle.Ahmed Bougacha2015-09-011-0/+4
| | | | | | | | | The code introduced in r244314 assumed that EXTRACT_VECTOR_ELT only takes constant indices, but it does accept variables. Bail out for those: we can't use them, as the shuffles we want to reconstruct do require constant masks. llvm-svn: 246594
* [ARM] Turn on by default interleaved access vectorizationSilviu Baranga2015-09-011-0/+2
| | | | | | | | | | | | | | Summary: This change turns on by default interleaved access vectorization on ARM, as it has shown to be beneficial on ARM. Reviewers: rengolin Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D12146 llvm-svn: 246541
* [Triple] Stop abusing a class to have only static methods and just useChandler Carruth2015-08-303-13/+13
| | | | | | | the namespace that we are already using for the enums that are produced by the parsing. llvm-svn: 246367
* [ARM] Hoist fabs/fneg above a conversion to float.James Molloy2015-08-291-1/+16
| | | | | | | | | | | | | | | | | | This is especially visible in softfp mode, for example in the implementation of libm fabs/fneg functions. If we have: %1 = vmovdrr r0, r1 %2 = fabs %1 then move the fabs before the vmovdrr: %1 = and r1, #0x7FFFFFFF %2 = vmovdrr r0, r1 This is never a lose, and could be a serious win because the vmovdrr may be followed by a vmovrrd, which would enable us to remove the conversion into FPRs completely. We already do this for f32, but not for f64. Tests are added for both. llvm-svn: 246360
* [CodeGen] Support (and default to) expanding READCYCLECOUNTER to 0.Ahmed Bougacha2015-08-281-30/+21
| | | | | | | | | | | For targets that didn't support this, this will let us respect the langref instead of failing to select. Note that we don't need to change the 32-bit x86/PPC lowerings (to account for the result type/# difference) because they're both custom and bypass type legalization. llvm-svn: 246258
* [WinEH] Add some support for code generating catchpadReid Kleckner2015-08-271-4/+4
| | | | | | | We can now run 32-bit programs with empty catch bodies. The next step is to change PEI so that we get funclet prologues and epilogues. llvm-svn: 246235
* [ARM] Use BranchProbability::scale() to scale an integer with a probability ↵Cong Hou2015-08-261-9/+3
| | | | | | | | | | in ARMBaseInstrInfo.cpp, Previously in isProfitableToIfCvt() in ARMBaseInstrInfo.cpp, the multiplication between an integer and a branch probability is done manually in an unsafe way that may lead to overflow. This patch corrects those cases by using BranchProbability's member function scale() to avoid overflow (which stores the intermediate result in int64). Differential Revision: http://reviews.llvm.org/D12295 llvm-svn: 246106
* FastISel: Use finishCondBranch() for ARM,Mips,PowerPC FastISelMatthias Braun2015-08-261-6/+3
| | | | | | Note that after this change branch probabilities are preserved now. llvm-svn: 245998
* MachineBasicBlock: Add liveins() method returning an iterator_rangeMatthias Braun2015-08-241-4/+2
| | | | llvm-svn: 245895
* [ARM] Use AEABI helpers for i64 div and remScott Douglass2015-08-242-5/+59
| | | | | | Differential Revision: http://reviews.llvm.org/D12232 llvm-svn: 245830
* [ARM] Refactor LowerDivRem before adding LowerREM (nfc)Scott Douglass2015-08-241-17/+36
| | | | | | Differential Revision: http://reviews.llvm.org/D12230 llvm-svn: 245829
* [ARM] Fix MachO CPU Subtype selectionVedant Kumar2015-08-211-12/+35
| | | | | | Differential Revision: http://reviews.llvm.org/D12040 llvm-svn: 245744
* [ARM] Don't try and custom lower a vNi64 SETCC.James Molloy2015-08-201-0/+6
| | | | | | | | It won't go well. We've already marked 64-bit SETCCs as non-Custom, but it's just possible that a SETCC has a legal result type but an illegal operand type. If this happens, bail out before we create unselectable nodes. Fixes PR24292. I tried to create a testcase but in 99% of cases we can't trigger this - not surprising that this bug has been latent since 2009. llvm-svn: 245577
* [ARM] Add instruction selection patterns for vmin/vmaxSilviu Baranga2015-08-192-6/+24
| | | | | | | | | | | | | | | | Summary: The mid-end was generating vector smin/smax/umin/umax nodes, but we were using vbsl to generatate the code. This adds the vmin/vmax patterns and a test to check that we are now generating vmin/vmax instructions. Reviewers: rengolin, jmolloy Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D12105 llvm-svn: 245439
* use minSize wrapper; NFCISanjay Patel2015-08-181-1/+1
| | | | | | | These were missed when other uses were switched over: http://llvm.org/viewvc/llvm-project?view=revision&revision=243994 llvm-svn: 245311
* Align SP adjustment in function getSPAdjustGuozhi Wei2015-08-171-2/+1
| | | | | | | This commit adds a new function TargetFrameLowering::alignSPAdjust and calls it from TargetInstrInfo::getSPAdjust. It fixes PR24142. llvm-svn: 245253
* [ARM] Fix crash when targetting CPU without NEONJames Molloy2015-08-171-3/+3
| | | | | | | | We emulate a scalar vmin/vmax with NEON instructions as they don't exist in the VFP ISA. So only mark these as legal when NEON is available. Found here: https://code.google.com/p/chromium/issues/detail?id=521671 llvm-svn: 245231
* [CostModel][ARM] Increase cost of insert/extract operationsSilviu Baranga2015-08-171-5/+12
| | | | | | | | | | | | | | | Summary: This change limits the minimum cost of an insert/extract element operation to 2 in cases where this would result in mixing of NEON and VFP code. Reviewers: rengolin Subscribers: mssimpso, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D12030 llvm-svn: 245225
* Rip out hand-rolled matching code for VMIN, VMAX, VMINNM and VMAXNMJames Molloy2015-08-171-194/+0
| | | | | | This is no longer needed - SDAGBuilder will do this for us. llvm-svn: 245197
* Remove redundant TargetFrameLowering::getFrameIndexOffset virtualJames Y Knight2015-08-152-7/+0
| | | | | | | | | | | function. This was the same as getFrameIndexReference, but without the FrameReg output. Differential Revision: http://reviews.llvm.org/D12042 llvm-svn: 245148
* Revert "[ARM] Fix MachO CPU Subtype selection"Renato Golin2015-08-141-35/+12
| | | | | | This reverts commit r245081, as it breaks many builds. llvm-svn: 245086
* [ARM] Fix MachO CPU Subtype selectionVedant Kumar2015-08-141-12/+35
| | | | | | | | | | This patch makes the Darwin ARM backend take advantage of TargetParser. It also teaches TargetParser about ARMV7K for the first time. This makes target triple parsing more consistent across llvm. Differential Revision: http://reviews.llvm.org/D11996 llvm-svn: 245081
* Revert "Centralize the information about which object format we are using."Rafael Espindola2015-08-141-8/+33
| | | | | | | | | | | | | | | | | | | | | This reverts commit r245047. It was failing on the darwin bots. The problem was that when running ./bin/llc -march=msp430 llc gets to if (TheTriple.getTriple().empty()) TheTriple.setTriple(sys::getDefaultTargetTriple()); Which means that we go with an arch of msp430 but a triple of x86_64-apple-darwin14.4.0 which fails badly. That code has to be updated to select a triple based on the value of march, but that is not a trivial fix. llvm-svn: 245062
* Centralize the information about which object format we are using.Rafael Espindola2015-08-141-33/+8
| | | | | | | | | | | Other than some places that were handling unknown as ELF, this should have no change. The test updates are because we were detecting arm-coff or x86_64-win64-coff as ELF targets before. It is not clear if the enum should live on the Triple. At least now it lives in a single location and should be easier to move somewhere else. llvm-svn: 245047
* [ARM] FMINNAN/FMAXNAN of f64 are not legal.James Molloy2015-08-131-2/+0
| | | | | | | | This was my error. We've got f32 marked as legal because they're simulated using a v2f32 instruction, but there's no equivalent for f64. This will get test coverage imminently when D12015 lands. llvm-svn: 244916
* [ARM] Allow vmin/vmax of scalars to be emitted without UseNEONForFP.James Molloy2015-08-131-2/+2
| | | | | | | | This overrides the default to more closely resemble the hand-crafted matching logic in ISelLowering. It makes sense, as there is no VFP equivalent of vmin or vmax, to use them when they're available even if in general VFP ops should be preferred. This should be NFC. llvm-svn: 244915
* [ARM] Reorganise and simplify thumb-1 load/store selectionJohn Brawn2015-08-132-169/+92
| | | | | | | | | | | | | | | | Other than PC-relative loads/store the patterns that match the various load/store addressing modes have the same complexity, so the order that they are matched is the order that they appear in the .td file. Rearrange the instruction definitions in ARMInstrThumb.td, and make use of AddedComplexity for PC-relative loads, so that the instruction matching order is the order that results in the simplest selection logic. This also makes register-offset load/store be selected when it should, as previously it was only selected for too-large immediate offsets. Differential Revision: http://reviews.llvm.org/D11800 llvm-svn: 244882
* PseudoSourceValue: Replace global manager with a manager in a machine function.Alex Lorenz2015-08-116-115/+116
| | | | | | | | | | | | | | | | | | | | | | This commit removes the global manager variable which is responsible for storing and allocating pseudo source values and instead it introduces a new manager class named 'PseudoSourceValueManager'. Machine functions now own an instance of the pseudo source value manager class. This commit also modifies the 'get...' methods in the 'MachinePointerInfo' class to construct pseudo source values using the instance of the pseudo source value manager object from the machine function. This commit updates calls to the 'get...' methods from the 'MachinePointerInfo' class in a lot of different files because those calls now need to pass in a reference to a machine function to those methods. This change will make it easier to serialize pseudo source values as it will enable me to transform the mips specific MipsCallEntry PseudoSourceValue subclass into two target independent subclasses. Reviewers: Akira Hatanaka llvm-svn: 244693
* [ARM] Match fminnan/fmaxnan for vector vmin/vmax instead of an intrinsicJames Molloy2015-08-112-4/+20
| | | | | | | | Lower Intrinsic::arm_neon_vmins/vmaxs to fminnan/fmaxnan and match that instead. This is important because SDAG will soon be able to select FMINNAN itself, so we need a unified lowering path for intrinsics and SDAG. NFCI. llvm-svn: 244593
* [ARM] Match fminnum/fmaxnum for vector vminnm/vmaxnm instead of an intrinsicJames Molloy2015-08-112-4/+16
| | | | | | | | Lower the intrinsic to a FMINNUM/FMAXNUM node and select that instead. This is important because soon SDAG will be able to select FMINNUM/FMAXNUM itself, so we need an integrated lowering path between SDAG and intrinsics. NFCI. llvm-svn: 244592
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