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* Struct byval: use the correct alignment for loads generated to loadManman Ren2013-10-071-1/+2
| | | | | | | | | | | | | | | from struct byval to registers. We used to pass 0 which means the alignment of PtrVT. Even when the alignment of the struct is smaller than 4, the LOADs would have alignment of 4, and further optimizations could combine the LOADs into a ldm, which would cause crash. The fix is to pass the alignment of the struct byval. rdar://problem/15144402 llvm-svn: 192126
* [ARM] Improve build attributes emission.Amara Emerson2013-10-076-56/+91
| | | | llvm-svn: 192111
* Remove getEHExceptionRegister and getEHHandlerRegister.Rafael Espindola2013-10-072-12/+0
| | | | | | They haven't been used for a long time. Patch by MathOnNapkins. llvm-svn: 192099
* ARM: allow cortex-m0 to use hint instructionsTim Northover2013-10-075-9/+22
| | | | | | | | | | | The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have been ported across to the v6M architecture. Fortunately, v6M seems to sit nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it fairly easily. rdar://problem/15144406 llvm-svn: 192097
* Remove some really nasty uses of hasRawTextSupport.Rafael Espindola2013-10-055-47/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When MC was first added, targets could use hasRawTextSupport to keep features working before they were added to the MC interface. The design goal of MC is to provide an uniform api for printing assembly and object files. Short of relaxations and other corner cases, a object file is just another representation of the assembly. It was never the intention that targets would keep doing things like if (hasRawTextSupport()) Set flags in one way. else Set flags in another way. When they do that they create two code paths and the object file is no longer just another representation of the assembly. This also then requires testing with llc -filetype=obj, which is extremelly brittle. This patch removes some of these hacks by replacing them with smaller ones. The ARM flag setting is trivial, so I just moved it to the constructor. For Mips, the patch adds two temporary hack directives that allow the assembly to represent the same things as the object file was already able to. The hope is that the mips developers will replace the hack directives with the same ones that gas uses and drop the -print-hack-directives flag. I will also try to implement a target streamer interface, so that we can move this out of the common code. In summary, for any new work, two rules of the thumb are * Don't use "llc -filetype=obj" in tests. * Don't add calls to hasRawTextSupport. llvm-svn: 192035
* ARM: optimizeSelect has to consider the previous register classMatthias Braun2013-10-041-4/+9
| | | | | | | | optimizeSelect folds (predicated) copy instructions, it must not ignore the original register class of the operand when replacing the register with the copies dest register. llvm-svn: 191963
* ARM: do not add a regmask for TAILJUMPsMatthias Braun2013-10-041-16/+18
| | | | | | | | | The jump doesn't really kill the registers, the following call does but we never get back anyway. This avoids some verify-machineinstrs problems when TAILJUMPs are if-converted. llvm-svn: 191962
* ARM: preserve undef flag in pseudo instruction expandersMatthias Braun2013-10-041-19/+14
| | | | | | | Copy over the whole register machine operand instead of creating a new one with an incomplete set of flags. llvm-svn: 191961
* [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.Amara Emerson2013-10-037-78/+126
| | | | | | Patch by Artyom Skrobov. llvm-svn: 191885
* ARM: support interrupt attributeTim Northover2013-10-018-21/+148
| | | | | | | | | | | This function-attribute modifies the callee-saved register list and function epilogue (specifically the return instruction) so that a routine is suitable for use as an interrupt-handler of the specified type without disrupting user-mode applications. rdar://problem/14207019 llvm-svn: 191766
* [ARM] Remove an unused function from the disassembler.Joey Gouly2013-10-011-11/+0
| | | | | | Pointed out by Joerg. llvm-svn: 191749
* [ARM] Introduce the 'sevl' instruction in ARMv8.Joey Gouly2013-10-015-29/+22
| | | | | | | This also removes the restriction on the immediate field of the 'hint' instruction. llvm-svn: 191744
* [ARM] Clean up ARMAsmParser::validateInstruction().Tilmann Scheller2013-09-301-38/+36
| | | | | | | | Fix some LLVM Coding Standards violations. No changes in functionality. llvm-svn: 191686
* [ARM] Assembler: ARM LDRD with writeback requires the base register to be ↵Tilmann Scheller2013-09-301-4/+19
| | | | | | | | | | different from the destination registers. See ARM ARM A8.8.72. Violating this constraint results in unpredictable behavior. llvm-svn: 191678
* Swift model: Fix uop description on some writesArnold Schwaighofer2013-09-301-2/+11
| | | | | | Those writes really need two/three uops. llvm-svn: 191677
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-302-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For targets that have instruction itineraries this means no change. Targets that move over to the new schedule model will use be able the new schedule module for instruction latencies in the if-converter (the logic is such that if there is no itineary we will use the new sched model for the latencies). Before, we queried "TTI->getInstructionLatency()" for the instruction latency and the extra prediction cost. Now, we query the TargetSchedule abstraction for the instruction latency and TargetInstrInfo for the extra predictation cost. The TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if an itinerary exists, otherwise it will use the new schedule model. ATTENTION: Out of tree targets! (I will also send out an email later to LLVMDev) This means, if your target implements unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost); and returns a value for "PredCost", you now also need to implement unsigned getPredictationCost(const MachineInstr *MI); (if your target uses the IfConversion.cpp pass) radar://15077010 llvm-svn: 191671
* Even more spelling fixes for "instruction".Robert Wilhelm2013-09-282-2/+2
| | | | llvm-svn: 191611
* ARM: Teach assembler to enforce constraints for ARM LDRD destination ↵Tilmann Scheller2013-09-271-1/+10
| | | | | | | | | | | | | | | | | | | register operands. As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints: LDRD<c> <Rt>, <Rt2>, ... (a) Rt must be even-numbered and not r14 (b) Rt2 must be R(t+1) If those two constraints are not met the result of executing the instruction will be unpredictable. Constraint (b) was already enforced, this commit adds support for constraint (a). Fixes rdar://14479793. llvm-svn: 191520
* Fix comment.Tilmann Scheller2013-09-271-1/+1
| | | | llvm-svn: 191505
* ARM: Teach assembler to enforce constraint for Thumb2 LDRD ↵Tilmann Scheller2013-09-271-0/+11
| | | | | | | | | | | | | | | | | (literal/immediate) destination register operands. LDRD<c> <Rt>, <Rt2>, <label> LDRD<c> <Rt>, <Rt2>, [<Rn>{, #+/-<imm>}] LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm> LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]! As specified in A8.8.72/A8.8.73 in the ARM ARM, the T1 encoding has a constraint which enforces that Rt != Rt2. If this constraint is not met the result of executing the instruction will be unpredictable. Fixes rdar://14479780. llvm-svn: 191504
* Fix PR 17372: Emitting PLD for stack address for ARM Thumb2Weiming Zhao2013-09-261-0/+7
| | | | | | | t2PLDi12, t2PLDi8, t2PLDs was omitted in Thumb2InstrInfo. This patch fixes it. llvm-svn: 191441
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-266-305/+495
| | | | | | Patch by Artyom Skrobov. llvm-svn: 191428
* Fix PR 17368: disable vector mul distribution for square of add/sub for ARMWeiming Zhao2013-09-251-0/+10
| | | | | | | | | | | | | | | | | | | | Generally, it is desirable to distribute (a + b) * c to a*c + b*c for ARM with VMLx forwarding, where a, b and c are vectors. However, for (a + b)*(a + b), distribution will result in one extra instruction. With distribution: x = a + b (add) y = a * x (mul) z = y + b * y (mla) Without distribution: x = a + b (add) z = x * x (mul) This patch checks if a mul is a square of add/sub. If yes, skip distribution. llvm-svn: 191410
* CriticalAntiDepBreaker is no longer needed for armv7 scheduling.Andrew Trick2013-09-251-3/+1
| | | | | | | | | | | | | | | | | This is being disabled because it is no longer needed for performance. It is only used by postRAscheduler which is also planned for removal, and it is implemented with an out-dated view of register liveness. It consideres aliases instead of register units, assumes valid kill flags, and assumes implicit uses on partial register defs. Kill flags and implicit operands are error prone and impossible to verify. We should gradually eliminate dependence on them in the postRA phases. Targets that still benefit from this should move to the MI scheduler. If that doesn't solve the problem, then we should add a hook to regalloc to optimize reload placement. llvm-svn: 191348
* [ARM] Split A/R class into separate subtarget features.Amara Emerson2013-09-235-23/+37
| | | | | | Patch by Bradley Smith. llvm-svn: 191202
* ISelDAG: spot chain cycles involving MachineNodesTim Northover2013-09-221-1/+3
| | | | | | | | | | | | | | | | | Previously, the DAGISel function WalkChainUsers was spotting that it had entered already-selected territory by whether a node was a MachineNode (amongst other things). Since it's fairly common practice to insert MachineNodes during ISelLowering, this was not the correct check. Looking around, it seems that other nodes get their NodeId set to -1 upon selection, so this makes sure the same thing happens to all MachineNodes and uses that characteristic to determine whether we should stop looking for a loop during selection. This should fix PR15840. llvm-svn: 191165
* Added support for generate DWARF .debug_aranges sections automatically.Richard Mitton2013-09-191-1/+1
| | | | llvm-svn: 191052
* [ARMv8] Add support for the v8 cryptography extensions.Amara Emerson2013-09-198-16/+142
| | | | llvm-svn: 190996
* [ARMv8] Add CRC instructions.Joey Gouly2013-09-183-1/+80
| | | | | | Patch by Bradley Smith! llvm-svn: 190928
* [ARM] Fix the deprecation of MCR encodings that map to CP15{ISB,DSB,DMB}.Joey Gouly2013-09-172-9/+27
| | | | llvm-svn: 190862
* ARM: Deduplicate ConstantPoolValues.Benjamin Kramer2013-09-162-47/+36
| | | | llvm-svn: 190779
* Replace some unnecessary vector copies with references.Benjamin Kramer2013-09-151-3/+3
| | | | llvm-svn: 190770
* Fix spelling.Robert Wilhelm2013-09-141-1/+1
| | | | llvm-svn: 190749
* [ARMv8] Change hasV8Fp to hasFPARMv8, and other command line optionsJoey Gouly2013-09-138-31/+31
| | | | | | to be more consistent. llvm-svn: 190692
* [ARMv8] Emit the proper .fpu directive.Joey Gouly2013-09-131-3/+6
| | | | | | Patch by Bradley Smith! llvm-svn: 190683
* Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-123-31/+27
| | | | | | | | | | | | | | | | | | | | | | The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. llvm-svn: 190598
* ARM: Use the PICADD opcode calculated.Jim Grosbach2013-09-101-2/+6
| | | | | | | | | | | | | | We were figuring out whether to use tPICADD or PICADD, then just using tPICADD unconditionally anyway. Oops. A testcase from someone familiar enough with ELF to produce one would be appreciated. The existing PIC testcase correctly verifies the .s generated, but that doesn't catch this bug, which only showed up in direct-to-object mode. http://llvm.org/bugs/show_bug.cgi?id=17180 llvm-svn: 190417
* Remove unused private member in ARMAsmPrinter.cpp.Logan Chien2013-09-101-1/+1
| | | | | | | This commit removes the unused "AttributeItem" from ObjectAttributeEmitter. llvm-svn: 190412
* [ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.Joey Gouly2013-09-094-36/+121
| | | | | | | | | IT blocks can only be one instruction lonf, and can only contain a subset of the 16 instructions. Patch by Artyom Skrobov! llvm-svn: 190309
* Generate compact unwind encoding from CFI directives.Bill Wendling2013-09-092-2/+5
| | | | | | | | | | | | | | | We used to generate the compact unwind encoding from the machine instructions. However, this had the problem that if the user used `-save-temps' or compiled their hand-written `.s' file (with CFI directives), we wouldn't generate the compact unwind encoding. Move the algorithm that generates the compact unwind encoding into the MCAsmBackend. This way we can generate the encoding whether the code is from a `.ll' or `.s' file. <rdar://problem/13623355> llvm-svn: 190290
* [ARMv8] Implement the new DMB/DSB operands.Joey Gouly2013-09-057-20/+27
| | | | | | | This removes the custom ISD Node: MEMBARRIER and replaces it with an intrinsic. llvm-svn: 190055
* Add AArch32 DCPS{1,2,3} and HLT instructions.Richard Barton2013-09-054-7/+47
| | | | | | | | | | | | | | | | | These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. llvm-svn: 190053
* Reverting 190043 for now.Tilmann Scheller2013-09-053-23/+3
| | | | | | | Solution is not sufficient to prevent 'mov pc, lr' being emitted for jump table code. Test case doesn't trigger the added functionality. llvm-svn: 190047
* ARM: Add GPR register class excluding LR for use with the ADR instruction.Tilmann Scheller2013-09-053-3/+23
| | | | | | | | | This improves code generation for jump tables by avoiding the emission of "mov pc, lr" which could fool the processor into believing this is a return from a function causing mispredicts. The code generation logic for jump tables uses ADR to materialize the address of the jump target. Patch by Daniel Stewart! llvm-svn: 190043
* ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane.Jim Grosbach2013-09-041-0/+7
| | | | | | | | | | | | | These instructions, such as vmul.f32, require the second source operand to be in D0-D15 rather than the full D0-D31. When optimizing, make sure to account for that by constraining the register class of a replacement virtual register to be compatible with the virtual register(s) it's replacing. I've been unsuccessful in creating a non-fragile regression test. This issue was detected by the LLVM nightly test suite running on an A15 (Bullet). PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093 llvm-svn: 189972
* Swift: Only build vldm/vstm with q register aligned register listsArnold Schwaighofer2013-09-041-1/+4
| | | | | | | | Unaligned vldm/vstm need more uops and therefore are slower in general on swift. radar://14522102 llvm-svn: 189961
* Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes ↵Silviu Baranga2013-09-041-78/+54
| | | | | | on Cortex-A9. This also makes the existing code more compact. llvm-svn: 189958
* Revert "Revert "ARM: Improve pattern for isel mul of vector by scalar.""Jim Grosbach2013-09-031-0/+11
| | | | | | | | | This reverts commit r189648. Fixes for the previously failing clang-side arm_neon_intrinsics test cases will be checked in separately. llvm-svn: 189841
* ARM: Default to the Swift CPU when targeting armv7s/thumbv7s.Tilmann Scheller2013-09-021-2/+7
| | | | | | | | Test cases adjusted accordingly. This fixes rdar://14871821. llvm-svn: 189766
* Revert 189756 for now, it doesn't match what rdar://14871821 really wants.Tilmann Scheller2013-09-021-7/+2
| | | | | | What we really want is to enable Swift by default for *v7s triples (and there already seems to be some logic which attempts to do that). In that case the iOS version doesn't matter. llvm-svn: 189763
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