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* ARM: add a couple more NEON predicates.Tim Northover2013-10-241-4/+4
| | | | | | | | The fused multiply instructions were added in VFPv4 but are still NEON instructions, in particular they shouldn't be available on a Cortex-M4 not matter how floaty it is. llvm-svn: 193342
* ARM: mark various aliases with their architecture requirements.Tim Northover2013-10-242-8/+12
| | | | | | | | | | If an alias inherits directly from InstAlias then it doesn't get any default "Requires" values, so llvm-mc will allow it even on architectures that don't support the underlying instruction. This tidies up the obvious VFP and NEON cases I found. llvm-svn: 193340
* ARM: Use non-VFP softcalls on embedded Darwinish targetsTim Northover2013-10-241-1/+1
| | | | | | | | | | | | | The compiler-rt functions __adddf3vfp and so on exist purely to allow Thumb1 code to make use of VFP instructions by switching back to ARM mode, they make no sense for M-class processors which don't even have an ARM mode. Given that justification, in practice this is a platform ABI decision so the actual check is based on that rather than CPU features. rdar://problem/15302004 llvm-svn: 193327
* ARM: fix assert on unpredictable POP instruction.Tim Northover2013-10-241-3/+2
| | | | | | | | | | | POP instructions are aliased to the ARM LDM variants but have different syntax. This caused two problems: we tried to access a non-existent operand to annotate the '!', and the error message didn't make much sense. With some vigorous hand-waving in the error message both problems can be fixed. llvm-svn: 193322
* Make ARM hint ranges consistent, and add tests for these rangesArtyom Skrobov2013-10-234-6/+26
| | | | llvm-svn: 193238
* ARM: provide diagnostics on more writeback LDM/STM instructionsTim Northover2013-10-222-17/+41
| | | | | | | | | | | | | | The set of circumstances where the writeback register is allowed to be in the list of registers is rather baroque, but I think this implements them all on the assembly parsing side. For disassembly, we still warn about an ARM-mode LDM even if the architecture revision is < v7 (the required architecture information isn't available). It's a silly instruction anyway, so hopefully no-one will mind. rdar://problem/15223374 llvm-svn: 193185
* ARM: Thumb2 copy for GPRPair needs to use thumb instructions.Jim Grosbach2013-10-221-1/+1
| | | | | | | | Use tMOVr instead of plain MOVr. rdar://15193017 llvm-svn: 193139
* ARM: Clean up copyPhysReg() a bit.Jim Grosbach2013-10-221-27/+47
| | | | | | No functional change, just cleaning things up for readability. llvm-svn: 193138
* Pure refactoring change.Richard Barton2013-10-181-73/+86
| | | | | | Patch by Artyom Skrobov. llvm-svn: 192977
* Add hint disassembly syntax for 16-bit Thumb hint instructions.Richard Barton2013-10-184-25/+23
| | | | | | Patch by Artyom Skrobov llvm-svn: 192972
* Add hardware division as a default feature on Cortex-A15. Also add test ↵Silviu Baranga2013-10-182-2/+3
| | | | | | cases to check this, and change diagnostics for the hwdiv-arm feature to something useful. llvm-svn: 192963
* 17309 ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targetsDavid Peixotto2013-10-171-7/+108
| | | | | | | | | | | | | | | | | | | | | | | | This commit implements the correct lowering of the COPY_STRUCT_BYVAL_I32 pseudo-instruction for thumb1 targets. Previously, the lowering of COPY_STRUCT_BYVAL_I32 generated the post-increment forms of ldr/ldrh/ldrb instructions. Thumb1 does not have the post-increment form of these instructions so the generated assembly contained invalid instructions. Passing the generated assembly to gcc caused it to complain with an error like this: Error: cannot honor width suffix -- `ldrb r3,[r0],#1' and the integrated assembler would generate an object file with an invalid instruction encoding. This commit contains a small test case that demonstrates the problem with thumb1 targets as well as an expanded test case that more throughly tests the lowering of byval struct passing for arm, thumb1, and thumb2 targets. llvm-svn: 192916
* Refactor lowering for COPY_STRUCT_BYVAL_I32David Peixotto2013-10-171-170/+460
| | | | | | | | | | | | | | | | | | This commit refactors the lowering of the COPY_STRUCT_BYVAL_I32 pseudo-instruction in the ARM backend. We introduce a new helper class that encapsulates all of the operations needed during the lowering. The operations are implemented for each subtarget in different subclasses. Currently only arm and thumb2 subtargets are supported. This refactoring was done to easily implement support for thumb1 subtargets. This initial patch does not add support for thumb1, but is only a refactoring. A follow on patch will implement the support for thumb1 subtargets. No intended functionality change. llvm-svn: 192915
* Add a MCAsmInfoELF class and factor some code into it.Rafael Espindola2013-10-162-3/+2
| | | | | | We had a MCAsmInfoCOFF, but no common class for all the ELF MCAsmInfos before. llvm-svn: 192760
* Struct byval: fix a copy-paste error for thumb2.Manman Ren2013-10-151-1/+1
| | | | | | PR17309 llvm-svn: 192730
* Add Cortex-A57 supportBernard Ogden2013-10-142-1/+10
| | | | llvm-svn: 192591
* Add subtarget feature support for Cortex-A53Bernard Ogden2013-10-143-4/+18
| | | | | | | Some previous implicit defaults have changed, for example FP and NEON are now on by default. llvm-svn: 192590
* [ARM] Fix FP ABI attributes with no VFP enabled.Amara Emerson2013-10-111-14/+12
| | | | llvm-svn: 192458
* ARM: Put isV8EligibleForIT into the llvm namespace. While there make it inline.Benjamin Kramer2013-10-101-2/+4
| | | | llvm-svn: 192350
* ARM: correct liveness flags during ARMLoadStoreOptTim Northover2013-10-101-0/+77
| | | | | | | | | | | | | | | | | | | | | | When we had a sequence like: s1 = VLDRS [r0, 1], Q0<imp-def> s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def> s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def> s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def> we were gathering the {s0, s1} loads below the s3 load. This is fine, but confused the verifier since now the s3 load had Q0<imp-use> with no definition above it. This should mark such uses <undef> as well. The liveness structure at the beginning and end of the block is unaffected, and the true sN definitions should prevent any dodgy reorderings being introduced elsewhere. rdar://problem/15124449 llvm-svn: 192344
* Flip the ownership of MCStreamer and MCTargetStreamer.Benjamin Kramer2013-10-091-1/+1
| | | | | | | MCStreamer now owns the target streamer. This prevents leaking the target streamer. llvm-svn: 192303
* Add a MCTargetStreamer interface.Rafael Espindola2013-10-085-58/+186
| | | | | | | | | | | | | This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. llvm-svn: 192181
* Struct byval: use the correct alignment for loads generated to loadManman Ren2013-10-071-1/+2
| | | | | | | | | | | | | | | from struct byval to registers. We used to pass 0 which means the alignment of PtrVT. Even when the alignment of the struct is smaller than 4, the LOADs would have alignment of 4, and further optimizations could combine the LOADs into a ldm, which would cause crash. The fix is to pass the alignment of the struct byval. rdar://problem/15144402 llvm-svn: 192126
* [ARM] Improve build attributes emission.Amara Emerson2013-10-076-56/+91
| | | | llvm-svn: 192111
* Remove getEHExceptionRegister and getEHHandlerRegister.Rafael Espindola2013-10-072-12/+0
| | | | | | They haven't been used for a long time. Patch by MathOnNapkins. llvm-svn: 192099
* ARM: allow cortex-m0 to use hint instructionsTim Northover2013-10-075-9/+22
| | | | | | | | | | | The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have been ported across to the v6M architecture. Fortunately, v6M seems to sit nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it fairly easily. rdar://problem/15144406 llvm-svn: 192097
* Remove some really nasty uses of hasRawTextSupport.Rafael Espindola2013-10-055-47/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When MC was first added, targets could use hasRawTextSupport to keep features working before they were added to the MC interface. The design goal of MC is to provide an uniform api for printing assembly and object files. Short of relaxations and other corner cases, a object file is just another representation of the assembly. It was never the intention that targets would keep doing things like if (hasRawTextSupport()) Set flags in one way. else Set flags in another way. When they do that they create two code paths and the object file is no longer just another representation of the assembly. This also then requires testing with llc -filetype=obj, which is extremelly brittle. This patch removes some of these hacks by replacing them with smaller ones. The ARM flag setting is trivial, so I just moved it to the constructor. For Mips, the patch adds two temporary hack directives that allow the assembly to represent the same things as the object file was already able to. The hope is that the mips developers will replace the hack directives with the same ones that gas uses and drop the -print-hack-directives flag. I will also try to implement a target streamer interface, so that we can move this out of the common code. In summary, for any new work, two rules of the thumb are * Don't use "llc -filetype=obj" in tests. * Don't add calls to hasRawTextSupport. llvm-svn: 192035
* ARM: optimizeSelect has to consider the previous register classMatthias Braun2013-10-041-4/+9
| | | | | | | | optimizeSelect folds (predicated) copy instructions, it must not ignore the original register class of the operand when replacing the register with the copies dest register. llvm-svn: 191963
* ARM: do not add a regmask for TAILJUMPsMatthias Braun2013-10-041-16/+18
| | | | | | | | | The jump doesn't really kill the registers, the following call does but we never get back anyway. This avoids some verify-machineinstrs problems when TAILJUMPs are if-converted. llvm-svn: 191962
* ARM: preserve undef flag in pseudo instruction expandersMatthias Braun2013-10-041-19/+14
| | | | | | | Copy over the whole register machine operand instead of creating a new one with an incomplete set of flags. llvm-svn: 191961
* [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.Amara Emerson2013-10-037-78/+126
| | | | | | Patch by Artyom Skrobov. llvm-svn: 191885
* ARM: support interrupt attributeTim Northover2013-10-018-21/+148
| | | | | | | | | | | This function-attribute modifies the callee-saved register list and function epilogue (specifically the return instruction) so that a routine is suitable for use as an interrupt-handler of the specified type without disrupting user-mode applications. rdar://problem/14207019 llvm-svn: 191766
* [ARM] Remove an unused function from the disassembler.Joey Gouly2013-10-011-11/+0
| | | | | | Pointed out by Joerg. llvm-svn: 191749
* [ARM] Introduce the 'sevl' instruction in ARMv8.Joey Gouly2013-10-015-29/+22
| | | | | | | This also removes the restriction on the immediate field of the 'hint' instruction. llvm-svn: 191744
* [ARM] Clean up ARMAsmParser::validateInstruction().Tilmann Scheller2013-09-301-38/+36
| | | | | | | | Fix some LLVM Coding Standards violations. No changes in functionality. llvm-svn: 191686
* [ARM] Assembler: ARM LDRD with writeback requires the base register to be ↵Tilmann Scheller2013-09-301-4/+19
| | | | | | | | | | different from the destination registers. See ARM ARM A8.8.72. Violating this constraint results in unpredictable behavior. llvm-svn: 191678
* Swift model: Fix uop description on some writesArnold Schwaighofer2013-09-301-2/+11
| | | | | | Those writes really need two/three uops. llvm-svn: 191677
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-302-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For targets that have instruction itineraries this means no change. Targets that move over to the new schedule model will use be able the new schedule module for instruction latencies in the if-converter (the logic is such that if there is no itineary we will use the new sched model for the latencies). Before, we queried "TTI->getInstructionLatency()" for the instruction latency and the extra prediction cost. Now, we query the TargetSchedule abstraction for the instruction latency and TargetInstrInfo for the extra predictation cost. The TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if an itinerary exists, otherwise it will use the new schedule model. ATTENTION: Out of tree targets! (I will also send out an email later to LLVMDev) This means, if your target implements unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost); and returns a value for "PredCost", you now also need to implement unsigned getPredictationCost(const MachineInstr *MI); (if your target uses the IfConversion.cpp pass) radar://15077010 llvm-svn: 191671
* Even more spelling fixes for "instruction".Robert Wilhelm2013-09-282-2/+2
| | | | llvm-svn: 191611
* ARM: Teach assembler to enforce constraints for ARM LDRD destination ↵Tilmann Scheller2013-09-271-1/+10
| | | | | | | | | | | | | | | | | | | register operands. As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints: LDRD<c> <Rt>, <Rt2>, ... (a) Rt must be even-numbered and not r14 (b) Rt2 must be R(t+1) If those two constraints are not met the result of executing the instruction will be unpredictable. Constraint (b) was already enforced, this commit adds support for constraint (a). Fixes rdar://14479793. llvm-svn: 191520
* Fix comment.Tilmann Scheller2013-09-271-1/+1
| | | | llvm-svn: 191505
* ARM: Teach assembler to enforce constraint for Thumb2 LDRD ↵Tilmann Scheller2013-09-271-0/+11
| | | | | | | | | | | | | | | | | (literal/immediate) destination register operands. LDRD<c> <Rt>, <Rt2>, <label> LDRD<c> <Rt>, <Rt2>, [<Rn>{, #+/-<imm>}] LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm> LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]! As specified in A8.8.72/A8.8.73 in the ARM ARM, the T1 encoding has a constraint which enforces that Rt != Rt2. If this constraint is not met the result of executing the instruction will be unpredictable. Fixes rdar://14479780. llvm-svn: 191504
* Fix PR 17372: Emitting PLD for stack address for ARM Thumb2Weiming Zhao2013-09-261-0/+7
| | | | | | | t2PLDi12, t2PLDi8, t2PLDs was omitted in Thumb2InstrInfo. This patch fixes it. llvm-svn: 191441
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-266-305/+495
| | | | | | Patch by Artyom Skrobov. llvm-svn: 191428
* Fix PR 17368: disable vector mul distribution for square of add/sub for ARMWeiming Zhao2013-09-251-0/+10
| | | | | | | | | | | | | | | | | | | | Generally, it is desirable to distribute (a + b) * c to a*c + b*c for ARM with VMLx forwarding, where a, b and c are vectors. However, for (a + b)*(a + b), distribution will result in one extra instruction. With distribution: x = a + b (add) y = a * x (mul) z = y + b * y (mla) Without distribution: x = a + b (add) z = x * x (mul) This patch checks if a mul is a square of add/sub. If yes, skip distribution. llvm-svn: 191410
* CriticalAntiDepBreaker is no longer needed for armv7 scheduling.Andrew Trick2013-09-251-3/+1
| | | | | | | | | | | | | | | | | This is being disabled because it is no longer needed for performance. It is only used by postRAscheduler which is also planned for removal, and it is implemented with an out-dated view of register liveness. It consideres aliases instead of register units, assumes valid kill flags, and assumes implicit uses on partial register defs. Kill flags and implicit operands are error prone and impossible to verify. We should gradually eliminate dependence on them in the postRA phases. Targets that still benefit from this should move to the MI scheduler. If that doesn't solve the problem, then we should add a hook to regalloc to optimize reload placement. llvm-svn: 191348
* [ARM] Split A/R class into separate subtarget features.Amara Emerson2013-09-235-23/+37
| | | | | | Patch by Bradley Smith. llvm-svn: 191202
* ISelDAG: spot chain cycles involving MachineNodesTim Northover2013-09-221-1/+3
| | | | | | | | | | | | | | | | | Previously, the DAGISel function WalkChainUsers was spotting that it had entered already-selected territory by whether a node was a MachineNode (amongst other things). Since it's fairly common practice to insert MachineNodes during ISelLowering, this was not the correct check. Looking around, it seems that other nodes get their NodeId set to -1 upon selection, so this makes sure the same thing happens to all MachineNodes and uses that characteristic to determine whether we should stop looking for a loop during selection. This should fix PR15840. llvm-svn: 191165
* Added support for generate DWARF .debug_aranges sections automatically.Richard Mitton2013-09-191-1/+1
| | | | llvm-svn: 191052
* [ARMv8] Add support for the v8 cryptography extensions.Amara Emerson2013-09-198-16/+142
| | | | llvm-svn: 190996
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