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* AsmMatchers: Use unique_ptr to manage ownership of MCParsedAsmOperandDavid Blaikie2014-06-081-398/+349
| | | | | | | | | | | | I saw at least a memory leak or two from inspection (on probably untested error paths) and r206991, which was the original inspiration for this change. I ran this idea by Jim Grosbach a few weeks ago & he was OK with it. Since it's a basically mechanical patch that seemed sufficient - usual post-commit review, revert, etc, as needed. llvm-svn: 210427
* ARM: correct assertion for long-calls on WoASaleem Abdulrasool2014-06-071-2/+3
| | | | | | | | | | | COFF/PE, so the relocation model is never static. Loosen the assertion accordingly. The relocation can still be emitted properly, as it will be converted to an IMAGE_REL_ARM_ADDR32 which will be resolved by the loader taking the base relocation into account. This is necessary to permit the emission of long calls which can be controlled via the -mlong-calls option in the driver. llvm-svn: 210399
* Have TargetSelectionDAGInfo take a DataLayout initializer rather thanEric Christopher2014-06-061-3/+2
| | | | | | a TargetMachine since the only thing it wants is DataLayout. llvm-svn: 210366
* Add a new attribute called 'jumptable' that creates jump-instruction tables ↵Tom Roeder2014-06-052-0/+31
| | | | | | | | | | | | for functions marked with this attribute. It includes a pass that rewrites all indirect calls to jumptable functions to pass through these tables. This also adds backend support for generating the jump-instruction tables on ARM and X86. Note that since the jumptable attribute creates a second function pointer for a function, any function marked with jumptable must also be marked with unnamed_addr. llvm-svn: 210280
* Add a subtarget hook: enablePostMachineScheduler.Andrew Trick2014-06-042-0/+10
| | | | | | | | | | | | | | | As requested by AArch64 subtargets. Note that this will have no effect until the AArch64 target actually enables the pass like this: substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); As soon as armv7 switches over, PostMachineScheduler will become the default postRA scheduler, so this won't be necessary any more. Targets using the old postRA schedule would then do: substitutePass(&PostMachineSchedulerID, &PostRASchedulerID); llvm-svn: 210167
* ARMEB: Fix function return type f64Christian Pirker2014-06-011-0/+2
| | | | | | Reviewed at http://reviews.llvm.org/D3968 llvm-svn: 209990
* Update a couple of header inclusion guardsAlp Toker2014-05-311-2/+2
| | | | llvm-svn: 209980
* Have the TLOF creation take a Triple rather than needing a subtarget.Eric Christopher2014-05-311-4/+4
| | | | llvm-svn: 209937
* ARM: use AAPCS-style prologues for embedded MachO.Tim Northover2014-05-302-10/+13
| | | | | | | | | | | | | | | Darwin prologues save their GPRs in two stages: a narrow push of r0-r7 & lr, followed by a wide push of the remaining registers if there are any. AAPCS uses a single push.w instruction. It turns out that, on average, enough registers get pushed that code is smaller in the AAPCS prologue, which is a nice property for M-class programmers. They also have other options available for back-traces, so can hopefully deal with the fact that FP & LR aren't adjacent in memory. rdar://problem/15909583 llvm-svn: 209895
* ARM & AArch64: make use of common cmpxchg idioms after expansionTim Northover2014-05-301-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | The C and C++ semantics for compare_exchange require it to return a bool indicating success. This gets mapped to LLVM IR which follows each cmpxchg with an icmp of the value loaded against the desired value. When lowered to ldxr/stxr loops, this extra comparison is redundant: its results are implicit in the control-flow of the function. This commit makes two changes: it replaces that icmp with appropriate PHI nodes, and then makes sure earlyCSE is called after expansion to actually make use of the opportunities revealed. I've also added -{arm,aarch64}-enable-atomic-tidy options, so that existing fragile tests aren't perturbed too much by the change. Many of them either rely on undef/unreachable too pervasively to be restored to something well-defined (particularly while making sure they test the same obscure assert from many years ago), or depend on a particular CFG shape, which is disrupted by SimplifyCFG. rdar://problem/16227836 llvm-svn: 209883
* [ARM] Emit correct build attributes for the relocation models.Amara Emerson2014-05-271-0/+14
| | | | | | Patch by Asiri Rathnayake. llvm-svn: 209656
* ARM: teach AAPCS-VFP to deal with Cortex-M4.Tim Northover2014-05-272-13/+21
| | | | | | | | | | | Cortex-M4 only has single-precision floating point support, so any LLVM "double" type will have been split into 2 i32s by now. Fortunately, the consecutive-register framework turns out to be precisely what's needed to reconstruct the double and follow AAPCS-VFP correctly! rdar://problem/17012966 llvm-svn: 209650
* Segmented stacks: omit __morestack call when there's no frame.Tim Northover2014-05-221-2/+6
| | | | | | Patch by Florian Zeitz llvm-svn: 209436
* ARM: introduce llvm.arm.undefined intrinsicSaleem Abdulrasool2014-05-223-5/+5
| | | | | | | | | | | | This intrinsic permits the emission of platform specific undefined sequences. ARM has reserved the 0xde opcode which takes a single integer parameter (ignored by the CPU). This permits the operating system to implement custom behaviour on this trap. The llvm.arm.undefined intrinsic is meant to provide a means for generating the target specific behaviour from the frontend. This is particularly useful for Windows on ARM which has made use of a series of these special opcodes. llvm-svn: 209390
* Override runOnMachineFunction for ARMISelDAGToDAG so that we canEric Christopher2014-05-221-0/+7
| | | | | | reset the subtarget on each function. llvm-svn: 209386
* Fix typo.Eric Christopher2014-05-221-1/+1
| | | | llvm-svn: 209377
* MC: correct IMAGE_REL_ARM_MOV32T relocation emissionSaleem Abdulrasool2014-05-212-6/+7
| | | | | | | | | | | | This corrects the emission of IMAGE_REL_ARM_MOV32T relocations. Previously, we were avoiding the high portion of the relocation too early. If there was a section-relative relocation with an offset greater than 16-bits (65535), you would end up truncating the high order bits of the offset. Allow the current relocation representation to flow through out the MC layer to the object writer. Use the new ability to restrict recorded relocations to avoid emitting the relocation into the final object. llvm-svn: 209337
* ARM: correct bundle generation for MOV32T relocationsSaleem Abdulrasool2014-05-211-7/+3
| | | | | | | | | | | | | | | | | | | | | | | Although the previous code would construct a bundle and add the correct elements to it, it would not finalise the bundle. This resulted in the InternalRead markers not being added to the MachineOperands nor, more importantly, the externally visible defs to the bundle itself. So, although the bundle was not exposing the def, the generated code would be correct because there was no optimisations being performed. When optimisations were enabled, the post register allocator would kick in, and the hazard recognizer would reorder operations around the load which would define the value being operated upon. Rather than manually constructing the bundle, simply construct and finalise the bundle via the finaliseBundle call after both MIs have been emitted. This improves the code generation with optimisations where IMAGE_REL_ARM_MOV32T relocations are emitted. The changes to the other tests are the result of the bundle generation preventing the scheduler from hoisting the moves across the loads. The net effect of the generated code is equivalent, but, is much more identical to what is actually being lowered. llvm-svn: 209267
* ARMEB: Additional test files for ARM fixupsChristian Pirker2014-05-201-1/+4
| | | | llvm-svn: 209200
* SDAG: Legalize vector BSWAP into a shuffle if the shuffle is legal but the ↵Benjamin Kramer2014-05-191-0/+2
| | | | | | | | | | bswap not. - On ARM/ARM64 we get a vrev because the shuffle matching code is really smart. We still unroll anything that's not v4i32 though. - On X86 we get a pshufb with SSSE3. Required more cleverness in isShuffleMaskLegal. - On PPC we get a vperm for v8i16 and v4i32. v2i64 is unrolled. llvm-svn: 209123
* ARM: make libcall setup more table drivenSaleem Abdulrasool2014-05-181-161/+100
| | | | | | | | | Rather than create a series of function calls to setup the library calls, create a table with the information and just use the table to drive the configuration of the library calls. This makes it easier to both inspect the list as well as to modify it. NFC. llvm-svn: 209089
* ARM: improve WoA ABI conformance for frame registerSaleem Abdulrasool2014-05-181-3/+7
| | | | | | | | | Windows on ARM uses R11 for the frame pointer even though the environment is a pure Thumb-2, thumb-only environment. Replicate this behaviour to improve Windows ABI compatibility. This register is used for fast stack walking, and thus is part of the Windows ABI. llvm-svn: 209085
* ARM: consolidate frame pointer register knowledgeSaleem Abdulrasool2014-05-181-3/+5
| | | | | | | | | | | Use the ARMBaseRegisterInfo to query the frame register. The base register info is aware of the frame register that is used for the frame pointer. Use that to determine the frame register rather than duplicating the knowledge. Although, the code path is slightly different in that it may return SP, that can only occur if the frame pointer has been omitted in the machine function, which is supposed to contain the desired value in that case. llvm-svn: 209084
* Target: remove old constructors for CallLoweringInfoSaleem Abdulrasool2014-05-172-35/+26
| | | | | | | | | | This is mostly a mechanical change changing all the call sites to the newer chained-function construction pattern. This removes the horrible 15-parameter constructor for the CallLoweringInfo in favour of setting properties of the call via chained functions. No functional change beyond the removal of the old constructors are intended. llvm-svn: 209082
* ARM: whitespaceSaleem Abdulrasool2014-05-171-3/+3
| | | | | | Remove some whitespace. NFC. llvm-svn: 209079
* ARM: use the proper target object format for WoASaleem Abdulrasool2014-05-171-1/+2
| | | | | | | | WoA uses COFF, not ELF. ARMISelLowering::createTLOF would previously return ELF for any non-MachO platform. This was a missed site when the original change for target format support for Windows on ARM was done. llvm-svn: 209057
* Re-enable inline memcpy expansion for Thumb1.James Molloy2014-05-162-6/+5
| | | | | | Patch by Moritz Roth! llvm-svn: 208994
* Fix the Load/Store optimization pass to work with Thumb1.James Molloy2014-05-162-38/+238
| | | | | | Patch by Moritz Roth! llvm-svn: 208992
* Enable the Load/Store optimization pass for Thumb1 but make it return ↵James Molloy2014-05-162-8/+14
| | | | | | | | immediately for now. Patch by Moritz Roth! llvm-svn: 208991
* Fix a few comment typos and style issues.James Molloy2014-05-161-16/+17
| | | | | | Patch by Moritz Roth! llvm-svn: 208990
* ARM: add some integer/floating point conversion libcallsSaleem Abdulrasool2014-05-161-0/+22
| | | | | | | | Add some Windows on ARM specific library calls. These are provided by msvcrt, and can be used to perform integer to floating-point conversions (and vice-versa) mirroring similar functions in the RTABI. llvm-svn: 208949
* TableGen/ARM64: print aliases even if they have syntax variants.Tim Northover2014-05-151-2/+2
| | | | | | | To get at least one use of the change (and some actual tests) in with its commit, I've enabled the AArch64 & ARM64 NEON mov aliases. llvm-svn: 208867
* Fix some dyslexia in an assert messageJonathan Roelofs2014-05-151-2/+2
| | | | llvm-svn: 208842
* Rename ComputeMaskedBits to computeKnownBits. "Masked" has beenJay Foad2014-05-142-12/+12
| | | | | | inappropriate since it lost its Mask parameter in r154011. llvm-svn: 208811
* ARM-BE: test files for vector argument passingChristian Pirker2014-05-141-1/+2
| | | | | | Reviewed at http://reviews.llvm.org/D3766 llvm-svn: 208793
* ARM: implement support for the UDF mnemonicSaleem Abdulrasool2014-05-144-2/+37
| | | | | | | | | | | | | | The UDF instruction is a reserved undefined instruction space. The assembler mnemonic was introduced with ARM ARM rev C.a. The instruction is not predicated and the immediate constant is ignored by the CPU. Add support for the three encodings for this instruction. The changes to the invalid instruction test is due to the fact that the invalid instructions actually overlap with the undefined instruction. Introduction of the new instruction results in a partial decode as an undefined sequence. Drop the tests as they are invalid instruction patterns anyways. llvm-svn: 208751
* ARMEB: Fix byte order of EH frame unwinding instructions, with modified test ↵Christian Pirker2014-05-131-4/+14
| | | | | | | | | | | | file This commit was already commited as revision rL208689 and discussd in phabricator revision D3704. But the test file was crashing on OS X and windows. I fixed the test file in the same way as in rL208340. llvm-svn: 208711
* Revert "ARMEB: Fix byte order of EH frame unwinding instructions"Rafael Espindola2014-05-131-14/+4
| | | | | | | | This reverts commit r208689. The test was crashing on OS X and windows. llvm-svn: 208704
* ARMEB: Fix byte order of EH frame unwinding instructionsChristian Pirker2014-05-131-4/+14
| | | | llvm-svn: 208689
* Add support bswap16 to/from memory compiling to rev16 on ARM/ThumbLouis Gerbarg2014-05-122-0/+17
| | | | | | | | | | | The current patterns for REV16 misses mostn __builtin_bswap16() due to legalization promoting the operands to from load/stores toi32s and then truncing/extending them. This patch adds new patterns that catch the resultant DAGs and codegens them to rev16 instructions. Tests included. rdar://15353652 llvm-svn: 208620
* ARM: Implement big endian bit-conversion for NEON typeChristian Pirker2014-05-123-56/+142
| | | | llvm-svn: 208538
* Pass the value type to TLI::getRegisterByNameHal Finkel2014-05-112-2/+3
| | | | | | | | | | | | | We must validate the value type in TLI::getRegisterByName, because if we don't and the wrong type was used with the IR intrinsic, then we'll assert (because we won't be able to find a valid register class with which to construct the requested copy operation). For PPC64, additionally, the type information is necessary to decide between the 64-bit register and the 32-bit subregister. No functionality change. llvm-svn: 208508
* Add 'override' to getRegisterByName in *ISelLowering.hHal Finkel2014-05-111-1/+1
| | | | | | No functionality change intended. llvm-svn: 208507
* Add custom lowering for add/sub with overflow intrinsics to ARMLouis Gerbarg2014-05-092-0/+97
| | | | | | | | | | | | | This patch adds support to ARM for custom lowering of the llvm.{u|s}add.with.overflow.i32 intrinsics for i32/i64. This is particularly useful for handling idiomatic saturating math functions as generated by InstCombineCompare. Test cases included. rdar://14853450 llvm-svn: 208435
* ARM: HFAs must be passed in consecutive registersOliver Stannard2014-05-094-25/+217
| | | | | | | | | | When using the ARM AAPCS, HFAs (Homogeneous Floating-point Aggregates) must be passed in a block of consecutive floating-point registers, or on the stack. This means that unused floating-point registers cannot be back-filled with part of an HFA, however this can currently happen. This patch, along with the corresponding clang patch (http://reviews.llvm.org/D3083) prevents this. llvm-svn: 208413
* ARM: support PIC on Windows on ARMSaleem Abdulrasool2014-05-092-2/+27
| | | | | | | | Handle lowering of global addresses for PIC mode compilation on Windows. Always use the movw/movt load to load the address as Windows on ARM requires ARMv7+ and is a pure Thumb environment. llvm-svn: 208385
* ARM big endian function argument passingChristian Pirker2014-05-081-11/+30
| | | | llvm-svn: 208316
* ARM: support FK_SecRel_2 relocations on WoASaleem Abdulrasool2014-05-082-0/+6
| | | | | | | | This adds FK_SecRel_2 relocation support to ARM. This enables the building of object files for armv7-windows-msvc which enables CodeView line tables for debugging as opposed to armv7-windows-itanium which currently uses DWARF. llvm-svn: 208273
* Remove the UseCFI option from createAsmStreamer.Rafael Espindola2014-05-072-7/+4
| | | | | | We were already always passing true, this just removes the option. llvm-svn: 208205
* Allow using normal .eh_frame based unwinding on ARM. Use the sameJoerg Sonnenberger2014-05-072-1/+13
| | | | | | encodings as x86. Use this exception model for NetBSD. llvm-svn: 208166
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