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* ARM: support direct f16 <-> f64 conversionsTim Northover2014-07-172-7/+21
| | | | | | ARMv8 has instructions to handle it, otherwise a libcall is needed. llvm-svn: 213254
* CodeGen: extend f16 conversions to permit types > float.Tim Northover2014-07-172-4/+4
| | | | | | | | | | | | | | | | | | | This makes the two intrinsics @llvm.convert.from.f16 and @llvm.convert.to.f16 accept types other than simple "float". This is only strictly needed for the truncate operation, since otherwise double rounding occurs and there's no way to represent the strict IEEE conversion. However, for symmetry we allow larger types in the extend too. During legalization, we can expand an "fp16_to_double" operation into two extends for convenience, but abort when the truncate isn't legal. A new libcall is probably needed here. Even after this commit, various target tweaks are needed to actually use the extended intrinsics. I've put these into separate commits for clarity, so there are no actual tests of f64 conversion here. llvm-svn: 213248
* [RegisterCoalescer] Moving the RegisterCoalescer subtarget hook onto the ↵Chris Bieneman2014-07-164-64/+67
| | | | | | TargetRegisterInfo instead of the TargetSubtargetInfo. llvm-svn: 213188
* Added documentation for SizeMultiplier in the ARM subtarget hook for ↵Chris Bieneman2014-07-161-2/+11
| | | | | | | | register coalescing. Also fixed some 80 col violations. No functional code changes. llvm-svn: 213169
* Move Post RA Scheduling flag bit into SchedMachineModelSanjay Patel2014-07-152-25/+3
| | | | | | | | | | | | | | | | | | | | | Refactoring; no functional changes intended Removed PostRAScheduler bits from subtargets (X86, ARM). Added PostRAScheduler bit to MCSchedModel class. This bit is set by a CPU's scheduling model (if it exists). Removed enablePostRAScheduler() function from TargetSubtargetInfo and subclasses. Fixed the existing enablePostMachineScheduler() method to use the MCSchedModel (was just returning false!). Added methods to TargetSubtargetInfo to allow overrides for AntiDepBreakMode, CriticalPathRCs, and OptLevel for PostRAScheduling. Added enablePostRAScheduler() function to PostRAScheduler class which queries the subtarget for the above values. Preserved existing scheduler behavior for ARM, MIPS, PPC, and X86: a. ARM overrides the CPU's postRA settings by enabling postRA for any non-Thumb or Thumb2 subtarget. b. MIPS overrides the CPU's postRA settings by enabling postRA for everything. c. PPC overrides the CPU's postRA settings by enabling postRA for everything. d. X86 is the only target that actually has postRA specified via sched model info. Differential Revision: http://reviews.llvm.org/D4217 llvm-svn: 213101
* [RegisterCoalescer] Add new subtarget hook allowing targets to opt-out of ↵Chris Bieneman2014-07-153-0/+73
| | | | | | | | | | coalescing. The coalescer is very aggressive at propagating constraints on the register classes, and the register allocator doesn’t know how to split sub-registers later to recover. This patch provides an escape valve for targets that encounter this problem to limit coalescing. This patch also implements such for ARM to lower register pressure when using lots of large register classes. This works around PR18825. llvm-svn: 213078
* Revert "Refactor ARM subarchitecture parsing"Renato Golin2014-07-081-78/+82
| | | | | | This reverts commit 7b4a6882467e7fef4516a0cbc418cbfce0fc6f6d. llvm-svn: 212521
* Refactor ARM subarchitecture parsingRenato Golin2014-07-071-82/+78
| | | | | | | | | According to a FIXME in ARMMCTargetDesc.cpp the ARM version parsing should be in the Triple helper class. Patch by: Gabor Ballabas llvm-svn: 212479
* ARM: properly lower dllimport'ed global valuesSaleem Abdulrasool2014-07-071-2/+23
| | | | | | | | | | | | | | This completes the handling for DLL import storage symbols when lowering instructions. A DLL import storage symbol must have an additional load performed prior to use. This is applicable to variables and functions. This is particularly important for non-function symbols as it is possible to handle function references by emitting a thunk which performs the translation from the unprefixed __imp_ symbol to the proper symbol (although, this is a non-optimal lowering). For a variable symbol, no such thunk can be accommodated. llvm-svn: 212431
* ARM: correctly mangle dllimport symbolsSaleem Abdulrasool2014-07-072-17/+40
| | | | | | | | Add support for tracking DLLImport storage class information on a per symbol basis in the ARM instruction selection. Use that information to correctly mangle the symbol (dllimport symbols are referenced via *__imp_<name>). llvm-svn: 212430
* ARM: unify symbol name retrievalSaleem Abdulrasool2014-07-071-5/+8
| | | | | | | | | | | Ensure that all paths that retrieve the symbol name go through GetARMGVSymbol rather than getSymbol. This is desirable so that any global symbol mangling can be centralised to this function. The motivation for this is handling of symbols that are marked as having dll import dll storage. Such a symbol requires an extra load that is currently handled in the backend and a __imp_ prefix on the symbol name. llvm-svn: 212429
* ARM: when falling back to scattered relocs, keep the type.Tim Northover2014-07-041-3/+7
| | | | | | | | | | The linker relies on relocation type info (e.g. is it a branch?) to perform the correct actions, so we should keep that even when we end up using a scattered relocation for whatever reason. rdar://problem/17553104 llvm-svn: 212333
* Move function dependent resetting of a subtarget variable out of theEric Christopher2014-07-048-26/+26
| | | | | | | | | | subtarget. This involved having the movt predicate take the current function - since we care about size in instruction selection for whether or not to use movw/movt take the function so we can check the attributes. This required adding the current MachineFunction to FastISel and propagating through. llvm-svn: 212309
* Remove caching of the target machine and initialization of theEric Christopher2014-07-031-10/+5
| | | | | | | subtarget from ARMISelDAGtoDAG. The former is unnecessary and the latter is initialized on each runOnMachineFunction. llvm-svn: 212297
* [ARM] Implement ISB memory barrier intrinsicYi Kong2014-07-032-7/+8
| | | | | | | Adds support for __builtin_arm_isb. Also corrects DSB and ISB instructions modelling by adding has-side-effects property. llvm-svn: 212276
* [DAG] Pass the argument list to the CallLoweringInfo via move semantics. NFCI.Juergen Ributzka2014-07-012-4/+5
| | | | | | | | The argument list vector is never used after it has been passed to the CallLoweringInfo and moving it to the CallLoweringInfo is cleaner and pretty much as cheap as keeping a pointer to it. llvm-svn: 212135
* ARM: take care not to set the ThumbFunc bit on TLS data symbolsScott Douglass2014-06-301-1/+2
| | | | | | | | This fixes LNT SingleSource/UnitTests/Threads with -mthumb. Differential Revision: http://reviews.llvm.org/D4324 llvm-svn: 212029
* ARM: use symbolic name for constantSaleem Abdulrasool2014-06-301-1/+1
| | | | | | | This just changes the constant value to the symbolic name corresponding to it. NFC. llvm-svn: 212011
* Remove extraneous includes from the target machines.Eric Christopher2014-06-261-8/+0
| | | | llvm-svn: 211800
* Move all of the ARM subtarget features down onto the subtargetEric Christopher2014-06-264-121/+102
| | | | | | rather than the target machine. llvm-svn: 211799
* Move the frame lowering constructors out of line to avoid circularEric Christopher2014-06-264-9/+9
| | | | | | includes. llvm-svn: 211798
* Added parsing co-processor names starting with "cr"Renato Golin2014-06-261-9/+17
| | | | | | | | | | Additional compliant GAS names for coprocessor register name are enabled for all instruction with parameter MCK_CoprocReg: LDC,LDC2,STC,STC2,CDP,CDP2,MCR,MCR2,MCRR,MCRR2,MRC,MRC2,MRRC,MRRC2 Patch by Andrey Kuharev. llvm-svn: 211776
* Move expression visitation logic up to MCStreamer.Rafael Espindola2014-06-252-3/+2
| | | | | | Remove the duplicate from MCRecordStreamer. No functionality change. llvm-svn: 211714
* Simplify the visitation of target expressions. No functionality change.Rafael Espindola2014-06-253-31/+5
| | | | llvm-svn: 211707
* ARM: Fix TPsoft for Thumb modeChristian Pirker2014-06-242-5/+13
| | | | | | Reviewed at http://reviews.llvm.org/D4230 llvm-svn: 211601
* ARMEB: Vector extend operationsChristian Pirker2014-06-232-20/+150
| | | | | | Reviewed at http://reviews.llvm.org/D4043 llvm-svn: 211520
* ARM: mark UBFX as not allowing PC.Tim Northover2014-06-231-2/+2
| | | | | | | | | Strictly, it's unpredictable. But we don't quite model that yet and an error is better than ignoring the issue. This one somehow got left out before though. rdar://problem/15997748 llvm-svn: 211490
* Allow a target to create a null streamer.Rafael Espindola2014-06-204-71/+41
| | | | | | | | | Targets can assume that a target streamer is present, so they have to be able to construct a null streamer in order to set the target streamer in it to. Fixes a crash when using the null streamer with arm. llvm-svn: 211358
* Emit the ARM build attributes ABI_PCS_wchar_t and ABI_enum_size.Oliver Stannard2014-06-201-0/+26
| | | | | | | Emit the ARM build attributes ABI_PCS_wchar_t and ABI_enum_size based on module flags metadata. llvm-svn: 211349
* Add Support to Recognize and Vectorize NON SIMD instructions in SLPVectorizer.Karthik Bhat2014-06-201-20/+47
| | | | | | | | | This patch adds support to recognize patterns such as fadd,fsub,fadd,fsub.../add,sub,add,sub... and vectorizes them as vector shuffles if they are profitable. These patterns of vector shuffle can later be converted to instructions such as addsubpd etc on X86. Thanks to Arnold and Hal for the reviews. http://reviews.llvm.org/D4015 llvm-svn: 211339
* Add a new subtarget hook for whether or not we'd like to enableEric Christopher2014-06-193-7/+13
| | | | | | | | | the atomic load linked expander pass to run for a particular subtarget. This requires a check of the subtarget and so save the TargetMachine rather than only TargetLoweringInfo and update all callers. llvm-svn: 211314
* Fix typosAlp Toker2014-06-191-1/+1
| | | | llvm-svn: 211304
* Convert some assert(0) to llvm_unreachable or fold an 'if' condition into ↵Craig Topper2014-06-192-4/+2
| | | | | | the assert. llvm-svn: 211254
* Move ARMJITInfo off of the TargetMachine and down onto the subtarget.Eric Christopher2014-06-189-24/+28
| | | | | | | | | This required untangling a mess of headers that included around. This a recommit of r210953 with a fix for the removed accessor for JITInfo. llvm-svn: 211233
* [ARM] [MC] Refactor the constant pool classesWeiming Zhao2014-06-181-136/+1
| | | | | | | | | | | ARMTargetStreamer implements ConstantPool and AssmeblerConstantPools to keep track of assembler-generated constant pools that are used for ldr-pseudo. When implementing ldr-pseudo for AArch64, these two classes can be reused. So this patch factors them out from ARM target to the general MC lib. llvm-svn: 211198
* Replace some assert(0)'s with llvm_unreachable.Craig Topper2014-06-182-2/+2
| | | | llvm-svn: 211141
* Fix memory leak of RegScavenger accidentally added in r211037.James Molloy2014-06-171-1/+3
| | | | llvm-svn: 211097
* ARM: intrinsic support for rbit.Jim Grosbach2014-06-161-0/+5
| | | | | | | | | We already have an ARMISD node. Create an intrinsic to map to it so we can add support for the frontend __rbit() intrinsic. rdar://9283021 llvm-svn: 211057
* Since the DataLayout is always found off of the subtarget go aheadEric Christopher2014-06-161-7/+3
| | | | | | and query the base target machine implementation for it. llvm-svn: 211055
* ARM: implement correct atomic operations on v7MTim Northover2014-06-161-8/+14
| | | | | | | | | | ARM v7M has ldrex/strex but not ldrexd/strexd. This means 32-bit operations should work as normal, but 64-bit ones are almost certainly doomed. Patch by Phoebe Buckheister. llvm-svn: 211042
* Refactor the disabling of Thumb-1 LDM/STM generationJames Molloy2014-06-162-7/+7
| | | | | | | | Originally I switched the LD/ST optimizer off in TargetMachine as it was previously, but Eric has suggested he'd prefer that it be short-circuited in the pass itself. No functionality change. llvm-svn: 211037
* ARMEB: Fix trunc store for vector typesChristian Pirker2014-06-161-1/+2
| | | | | | Reviewed at http://reviews.llvm.org/D4135 llvm-svn: 211010
* Temporarily revert r210953 in an attempt to bring the ARM buildbotsEric Christopher2014-06-159-26/+24
| | | | | | back. llvm-svn: 210996
* Remove InstrItineraryData off of the TargetMachine - it's alreadyEric Christopher2014-06-132-6/+2
| | | | | | on the subtarget and just forward the accessor. llvm-svn: 210955
* Move ARMJITInfo off of the TargetMachine and down onto the subtarget.Eric Christopher2014-06-139-21/+25
| | | | | | This required untangling a mess of headers that included around. llvm-svn: 210953
* The hazard recognizer only needs a subtarget, not a target machineEric Christopher2014-06-132-6/+7
| | | | | | so make it take one. Fix up all users accordingly. llvm-svn: 210948
* ARM: Fix fastcc calling convention for Thumb1Oliver Stannard2014-06-131-3/+3
| | | | | | | | When targetting Thumb1 on a processor which has a VFP unit (which is not accessible from Thumb1), we were converting the fastcc calling convention to AAPCS-VFP, which is not possible. llvm-svn: 210889
* Move ARMSelectionDAGInfo from the TargetMachine to the subtarget.Eric Christopher2014-06-134-7/+7
| | | | llvm-svn: 210862
* Move to a private function to initialize subtarget dependenciesEric Christopher2014-06-134-76/+87
| | | | | | | | so we can use initializer lists for the ARMSubtarget and then use this to initialize a moved DataLayout on the subtarget from the TargetMachine. llvm-svn: 210861
* Have ARMSelectionDAGInfo take a DataLayout as it's argument as theEric Christopher2014-06-123-14/+11
| | | | | | | DAG has access to the subtarget and TargetSelectionDAGInfo only needs a DataLayout. llvm-svn: 210859
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