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* Fix test failures caused by my so_reg refactoring.Owen Anderson2011-07-221-2/+2
| | | | llvm-svn: 135785
* ARM assembly parsing and encoding for SMC instruction.Jim Grosbach2011-07-222-3/+3
| | | | llvm-svn: 135782
* Clean up a few more comments.Jim Grosbach2011-07-221-5/+5
| | | | | | | These instruction definitions are for the assembler, too, not just the disassembler. llvm-svn: 135781
* Tidy up.Jim Grosbach2011-07-221-2/+1
| | | | llvm-svn: 135779
* Thumb assembly support for SETEND instruction.Jim Grosbach2011-07-222-16/+11
| | | | llvm-svn: 135778
* Tidy up.Jim Grosbach2011-07-221-1/+1
| | | | llvm-svn: 135777
* ARM assembly parsing and encoding for SETEND instruction.Jim Grosbach2011-07-222-6/+52
| | | | | | | Add parsing and diagnostics for malformed inputs. Tests for diagnostics and for correct encodings. llvm-svn: 135776
* Tidy up.Jim Grosbach2011-07-221-6/+2
| | | | llvm-svn: 135771
* Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn ↵Owen Anderson2011-07-2111-98/+258
| | | | | | necessitates a lot of changes to related bits. llvm-svn: 135722
* ARM Asm parser range checking for [0,31] immediates.Jim Grosbach2011-07-212-0/+14
| | | | llvm-svn: 135719
* ARM assembly parsing support for RSC instruction.Jim Grosbach2011-07-211-0/+13
| | | | | | | Add two-operand instruction aliases. Add parsing and encoding tests for variants of the instruction. llvm-svn: 135713
* ARM assembly parsing support for RSB instruction.Jim Grosbach2011-07-211-0/+14
| | | | | | | Add two-operand instruction aliases. Add parsing and encoding tests for variants of the instruction. llvm-svn: 135712
* Tidy up.Jim Grosbach2011-07-211-2/+0
| | | | llvm-svn: 135706
* ARM assembly parsing POP/PUSH mnemonics.Jim Grosbach2011-07-211-0/+6
| | | | | | | | Aliases for LDM/STM. The single-register versions should encode to LDR/STR with writeback, but we don't (yet) get that correct. Neither does Darwin's system assembler, though, so that's not a deal-breaker of a limitation. llvm-svn: 135702
* Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, ↵Owen Anderson2011-07-216-66/+329
| | | | | | allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
* ARM assembly parsing and encoding for PKHBT and PKHTB instructions.Jim Grosbach2011-07-213-0/+100
| | | | llvm-svn: 135682
* Convert ConstantExpr::getGetElementPtr andJay Foad2011-07-211-1/+1
| | | | | | ConstantExpr::getInBoundsGetElementPtr to use ArrayRef. llvm-svn: 135673
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-2029-192/+200
| | | | | | ARM MC code from target. llvm-svn: 135636
* ARM PKH shift ammount operand printing tweaks.Jim Grosbach2011-07-206-18/+39
| | | | | | | | | | Move the shift operator and special value (32 encoded as 0 for PKHTB) handling into the instruction printer. This cleans up a bit of the disassembler special casing for these instructions, more easily handles not printing the operand at all for "lsl #0" and prepares for correct asm parsing of these operands. llvm-svn: 135626
* Tidy up a bit.Jim Grosbach2011-07-203-12/+7
| | | | | | | Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename them to be a bit more descriptive that they're for the PKH instructions. llvm-svn: 135617
* ARM: Tidy up representation of PKH instruction.Jim Grosbach2011-07-205-37/+35
| | | | | | | | | The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't be also encoded as part of the shift value immediate. Otherwise we're able to represent invalid instructions, plus it needlessly complicates the representation. Preparatory work for asm parsing of these instructions. llvm-svn: 135616
* ARM assembly parsing of MUL instruction.Jim Grosbach2011-07-201-1/+2
| | | | | | | Correctly handle 's' bit and predication suffices. Add parsing and encoding tests. llvm-svn: 135596
* - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.Evan Cheng2011-07-203-11/+15
| | | | | | | | - Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. llvm-svn: 135580
* Add MCObjectFileInfo and sink the MCSections initialization code fromEvan Cheng2011-07-201-1/+0
| | | | | | | | TargetLoweringObjectFileImpl down to MCObjectFileInfo. TargetAsmInfo is done to one last method. It's *almost* gone! llvm-svn: 135569
* Tweak ARM assembly parsing and printing of MSR instruction.Jim Grosbach2011-07-193-8/+19
| | | | | | | | The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. llvm-svn: 135532
* ARM assembly parsing of MRS instruction.Jim Grosbach2011-07-192-7/+11
| | | | | | | Teach the parser to recognize the APSR and SPSR system register names. Add and update tests accordingly. llvm-svn: 135527
* Enhance the FixedLengthDecoder to be able to generate plausible-looking ↵Owen Anderson2011-07-191-2/+11
| | | | | | decoders for ARM. llvm-svn: 135524
* ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.Jim Grosbach2011-07-192-9/+8
| | | | | | Add range checking to the immediate operands. Update tests accordingly. llvm-svn: 135521
* ARM assembly parsing for MOV (register).Jim Grosbach2011-07-191-19/+21
| | | | | | | | Correct the handling of the 's' suffix when parsing ARM mode. It's only a truly separate opcode in Thumb. Add test cases to make sure we handle the s and condition suffices correctly, including diagnostics. llvm-svn: 135513
* Tidy up.Jim Grosbach2011-07-191-12/+8
| | | | llvm-svn: 135507
* Tighten conditional for 'mov' cc_out.Jim Grosbach2011-07-191-1/+2
| | | | | | | Make sure we only clobber the cc_out operand if it is indeed a default non-setting operand. llvm-svn: 135506
* ARM assembly parsing for MOV (immediate).Jim Grosbach2011-07-193-16/+63
| | | | | | | | Add range checking for the immediate operand and handle the "mov" mnemonic choosing between encodings based on the value of the immediate. Add tests for fixups, encoding choice and values, and diagnostic for out of range values. llvm-svn: 135500
* Remove unused code.Jim Grosbach2011-07-191-54/+3
| | | | | | cc_out and pred operands are added during parsing via custom C++ now. llvm-svn: 135497
* ARM range checking for so_imm operands in assembly parsing.Jim Grosbach2011-07-192-0/+15
| | | | llvm-svn: 135489
* Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng2011-07-194-27/+33
| | | | | | | (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. llvm-svn: 135468
* Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having ↵Owen Anderson2011-07-183-12/+40
| | | | | | multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler. llvm-svn: 135442
* Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions forEvan Cheng2011-07-182-2/+0
| | | | | | better location welcome). llvm-svn: 135438
* Mark the Darwin assembler workout as isCodeGenOnly, so that it doesn't cause ↵Owen Anderson2011-07-181-1/+1
| | | | | | decoding conflicts in the new-style disassembler. llvm-svn: 135434
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-183-20/+4
| | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. llvm-svn: 135424
* Re-apply r135319 with a fix for the constant island pass.Owen Anderson2011-07-183-48/+29
| | | | | | Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change. llvm-svn: 135414
* Migrate LLVM and Clang to use the new makeArrayRef(...) functions where ↵Frits van Bommel2011-07-181-12/+12
| | | | | | | | previously explicit non-default constructors were used. Mostly mechanical with some manual reformatting. llvm-svn: 135390
* land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner2011-07-186-37/+37
| | | | llvm-svn: 135375
* Revert r135319 in an attempt to get to unbreak testers.Owen Anderson2011-07-162-27/+48
| | | | llvm-svn: 135343
* Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and ↵Owen Anderson2011-07-152-48/+27
| | | | | | tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change. llvm-svn: 135319
* Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ↵Owen Anderson2011-07-155-19/+14
| | | | | | to simplify the path towards an auto-generated disassembler. llvm-svn: 135290
* Remove unnecessary duplicate instruction definitions that simply overloaded ↵Owen Anderson2011-07-151-9/+8
| | | | | | the type of VEXT. This can be achieved with a Pat definition, and is much more disassembler friendly. llvm-svn: 135283
* Eliminate "const" from extern const to fix breakeage since r135184 on msvc.NAKAMURA Takumi2011-07-151-1/+1
| | | | | | MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions. llvm-svn: 135269
* Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatestEvan Cheng2011-07-151-3/+3
| | | | | | | solution but it is a small step towards removing the horror that is TargetAsmInfo. llvm-svn: 135237
* Major update to CMake build to reflect changes in r135219 in theChandler Carruth2011-07-152-2/+6
| | | | | | | | | | | | backend. Moved some MCAsmInfo files down into the MCTargetDesc sublibraries, removed some (i suspect long) dead files from other parts of the CMake build, etc. Also copied the include directory hack from the Makefile. Finally, updated the lib deps. I spot checked this, and think its correct, but review appreciated there. llvm-svn: 135234
* Rename createAsmInfo to createMCAsmInfo and move registration code to ↵Evan Cheng2011-07-144-27/+29
| | | | | | MCTargetDesc to prepare for next round of changes. llvm-svn: 135219
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