summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM
Commit message (Collapse)AuthorAgeFilesLines
* Store sub-class lists as a bit vector.Jakob Stoklund Olesen2011-09-301-1/+1
| | | | | | | | | | | | | | This uses less memory and it reduces the complexity of sub-class operations: - hasSubClassEq() and friends become O(1) instead of O(N). - getCommonSubClass() becomes O(N) instead of O(N^2). In the future, TableGen will infer register classes. This makes it cheap to add them. llvm-svn: 140898
* Correct for my over-eager delete finger.Jim Grosbach2011-09-301-0/+1
| | | | llvm-svn: 140892
* Constify 'isLSDA' and move a method out-of-line.Bill Wendling2011-09-302-14/+20
| | | | llvm-svn: 140868
* ARM Darwin default relocation model is PIC.Jim Grosbach2011-09-301-2/+5
| | | | | | | This matches clang, so default options in llc and friends are now closer to clang's defaults. llvm-svn: 140863
* ARM Fixup valus for movt/movw are for the whole value.Jim Grosbach2011-09-301-7/+0
| | | | | | | | | Remove an assert that was expecting only the relevant 16bit portion for the fixup being handled. Also kill some dead code in the T2 portion. rdar://9653509 llvm-svn: 140861
* ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.Jim Grosbach2011-09-308-145/+128
| | | | | | | | | | | Encode the immediate into its 8-bit form as part of isel rather than later, which simplifies things for mapping the encoding bits, allows the removal of the custom disassembler decoding hook, makes the operand printer trivial, and prepares things more cleanly for handling these in the asm parser. rdar://10211428 llvm-svn: 140834
* Create a machine basic block in the constant pool and retrieve the symbol ↵Bill Wendling2011-09-292-0/+7
| | | | | | for an MBB. llvm-svn: 140824
* Support creating a constant pool value for a machine basic block.Bill Wendling2011-09-292-2/+30
| | | | | | | This is used when we want to take the address of a machine basic block, but it's not associated with a BB in LLVM IR. llvm-svn: 140823
* Target/ARM: Unbreak! CMake! Build!NAKAMURA Takumi2011-09-291-1/+0
| | | | llvm-svn: 140774
* Delete NEONMoveFix, now unused.Jakob Stoklund Olesen2011-09-293-149/+0
| | | | llvm-svn: 140773
* Use ExecutionDepsFix instead of NEONMoveFix.Jakob Stoklund Olesen2011-09-292-11/+21
| | | | | | | This enables NEON domain tracking across basic blocks, but should otherwise do the same thing. llvm-svn: 140772
* Move to ISelLowering.Bill Wendling2011-09-293-131/+0
| | | | llvm-svn: 140754
* Tighten a ARM dag combine condition to avoid an identity transformation, whichEvan Cheng2011-09-281-1/+1
| | | | | | | | ends up introducing a cycle in the DAG. rdar://10196296 llvm-svn: 140733
* Perform the lowering only if there are invokes.Bill Wendling2011-09-281-9/+19
| | | | llvm-svn: 140719
* Ahem...actually *add* the ARMSjLjLowering pass to the pass manager.Bill Wendling2011-09-281-1/+1
| | | | llvm-svn: 140718
* Check in a patch that has already been code reviewed by Owen that I'd ↵James Molloy2011-09-288-12/+128
| | | | | | | | | | | | forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. llvm-svn: 140696
* Unbreak CMake build.Ted Kremenek2011-09-272-2/+3
| | | | llvm-svn: 140655
* Implement TII::get/setExecutionDomain() for ARM.Jakob Stoklund Olesen2011-09-272-0/+59
| | | | llvm-svn: 140653
* ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.Jim Grosbach2011-09-271-0/+10
| | | | | | | | Add inst alias to handle these assembly forms. Add tests, too. rdar://10178799 llvm-svn: 140647
* This is the start of the new SjLj EH preparation pass, which will replace theBill Wendling2011-09-273-1/+122
| | | | | | | | | | | | | | | | | | | current IR-level pass. The old SjLj EH pass has some problems, especially with the new EH model. Most significantly, it violates some of the new restrictions the new model has. For instance, the 'dispatch' table wants to jump to the landing pad, but we cannot allow that because only an invoke's unwind edge can jump to a landing pad. This requires us to mangle the code something awful. In addition, we need to keep the now dead landingpad instructions around instead of CSE'ing them because the DWARF emitter uses that information (they are dead because no control flow edge will execute them - the control flow edge from an invoke's unwind is superceded by the edge coming from the dispatch). Basically, this pass belongs not at the IR level where SSA is king, but at the code-gen level, where we have more flexibility. llvm-svn: 140646
* Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().Jim Grosbach2011-09-272-2/+2
| | | | | | Naming conventions consistency. No functional change. llvm-svn: 140636
* Use existing function.Jakob Stoklund Olesen2011-09-271-13/+1
| | | | llvm-svn: 140615
* Remove extraneous commit garbage.Owen Anderson2011-09-261-2/+0
| | | | llvm-svn: 140581
* ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.Owen Anderson2011-09-263-3/+37
| | | | llvm-svn: 140560
* PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL ↵David Meyer2011-09-261-1/+3
| | | | | | 2011-06-09-TailCallByVal and 2010-11-04-BigByval llvm-svn: 140516
* Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset ↵Owen Anderson2011-09-231-1/+1
| | | | | | of #-0. llvm-svn: 140426
* Also match negative offsets for addrmode3 and addrmode5.Jakob Stoklund Olesen2011-09-231-2/+2
| | | | | | | | Math is hard, and isScaledConstantInRange() always returned false for negative constants. It was doing unsigned division of negative numbers before casting back to signed. llvm-svn: 140425
* Add more fixed bits to USAT16 encoding to filter out incorrect decodings.Owen Anderson2011-09-231-2/+2
| | | | llvm-svn: 140422
* Post-index loads/stores in still need to print the post-indexed immediate, ↵Owen Anderson2011-09-232-11/+11
| | | | | | even if it's zero, to distinguish them from non-post-indexed instructions. llvm-svn: 140420
* Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid ↵Owen Anderson2011-09-231-1/+1
| | | | | | testcases updated. llvm-svn: 140415
* Revert r140412. This affects more instructions than intended.Owen Anderson2011-09-231-1/+1
| | | | llvm-svn: 140413
* Thumb2 register-shifted-register loads cannot target the PC or the SP.Owen Anderson2011-09-231-1/+1
| | | | llvm-svn: 140412
* Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix ↵Owen Anderson2011-09-213-14/+0
| | | | | | other test failures I caused. llvm-svn: 140284
* Print out immediate offset versions of PC-relative load/store instructions ↵Owen Anderson2011-09-213-0/+27
| | | | | | as [pc, #123] rather than simply #123. llvm-svn: 140283
* These do not need to be conditional on the presence of CommentStream, as ↵Owen Anderson2011-09-211-12/+12
| | | | | | they have a fallback path now. llvm-svn: 140267
* Lower ARM adds/subs to add/sub after adding optional CPSR operand.Andrew Trick2011-09-216-142/+144
| | | | | | | | | | | | | This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. llvm-svn: 140228
* whitespaceAndrew Trick2011-09-211-4/+4
| | | | llvm-svn: 140227
* In the disassembler C API, be careful not to confuse the comment streamer ↵Owen Anderson2011-09-211-12/+12
| | | | | | that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on. llvm-svn: 140217
* Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 ↵Evan Cheng2011-09-201-3/+5
| | | | | | does not support Thumb2 dsp instructions. rdar://10152911. llvm-svn: 140181
* Restore hasPostISelHook tblgen flag.Andrew Trick2011-09-202-6/+8
| | | | | | | | | | No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. llvm-svn: 140160
* ARM isel bug fix for adds/subs operands.Andrew Trick2011-09-203-24/+63
| | | | | | | | | | | Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the full gamut of CPSR defs/uses including instructins whose "optional" cc_out operand is not really optional. This allowed removal of the hasPostISelHook to simplify the .td files and make the implementation more robust. Fixes rdar://10137436: sqlite3 miscompile llvm-svn: 140134
* whitespaceAndrew Trick2011-09-201-13/+13
| | | | llvm-svn: 140133
* Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.Jim Grosbach2011-09-202-3/+31
| | | | llvm-svn: 140125
* Thumb2 assembly parsing and encoding for USAX.Jim Grosbach2011-09-201-0/+2
| | | | llvm-svn: 140119
* Remove incorrect comments. These are not disassmebly only patterns.Jim Grosbach2011-09-201-12/+6
| | | | llvm-svn: 140116
* Thumb2 assembly parsing and encoding for UQASX/UQSAX.Jim Grosbach2011-09-201-0/+4
| | | | llvm-svn: 140111
* Thumb1 convenience aliases for disassembler round-trip testing. CPS instruction.Jim Grosbach2011-09-201-0/+8
| | | | llvm-svn: 140108
* Thumb CPS definition is not disassembler only.Jim Grosbach2011-09-201-2/+1
| | | | llvm-svn: 140106
* Thumb2 range check on CPS mode immediate.Jim Grosbach2011-09-191-1/+1
| | | | llvm-svn: 140105
* tMOVSr is not allowed in an IT block either.Owen Anderson2011-09-191-0/+1
| | | | llvm-svn: 140104
OpenPOWER on IntegriCloud