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* AArch64/ARM64: add specific diagnostic for MRS/MSR and enable tests.Tim Northover2014-04-302-1/+9
| | | | llvm-svn: 207667
* AArch64/ARM64: accept and print floating-point immediate 0 as "#0.0"Tim Northover2014-04-302-19/+41
| | | | | | | | | | It's been decided that in the future, the floating-point immediate in instructions like "fcmeq v0.2s, v1.2s, #0.0" will be canonically "0.0", which has been implemented on AArch64 already but not ARM64. This fixes that issue. llvm-svn: 207666
* [ARM64][fast-isel] Fast-isel doesn't know how to handle f128.Chad Rosier2014-04-301-1/+14
| | | | llvm-svn: 207659
* ARM64: print lsr instead of lsrv for variable shifts (etc)Tim Northover2014-04-301-13/+13
| | | | | | | The canonical syntax for shifts by a variable amount does not end with 'v', but that syntax should be supported as an alias (presumably for legacy reasons). llvm-svn: 207649
* ARM64: use 32-bit operations for uxtb & uxthTim Northover2014-04-301-3/+19
| | | | | | Testing will be enabled shortly with basic-a64-instructions.s llvm-svn: 207648
* AArch64/ARM64: allow smaller granule relocations on MOVZ/MOVNTim Northover2014-04-301-6/+6
| | | | | | Testing will be enabled shortly with basic-a64-instructions.s llvm-svn: 207647
* AArch64/ARM64: copy support for bCC instead of b.CC across.Tim Northover2014-04-301-0/+21
| | | | llvm-svn: 207646
* AArch64/ARM64: expunge CPSR from the sourcesTim Northover2014-04-3012-123/+125
| | | | | | | | | | | | AArch64 does not have a CPSR register in the same way that AArch32 does. Most of its compiler-relevant roles have been taken over by the more specific NZCV register (representing just the flags set by normal instructions). Its system control functions still remain, but are now under the pseudo-register referred to as "PSTATE". They're accessed via various MRS & MSR instructions described in the reference manual. llvm-svn: 207645
* AArch64/ARM64: use HS instead of CS & LO instead of CC.Tim Northover2014-04-304-20/+20
| | | | | | | | | On instructions using the NZCV register, a couple of conditions have dual representations: HS/CS and LO/CC (meaning unsigned-higher-or-same/carry-set and unsigned-lower/carry-clear). The first of these is more descriptive in most circumstances, so we should print it. llvm-svn: 207644
* ARM64: accept ELF-relocated load/store insts without a #.Tim Northover2014-04-301-0/+1
| | | | | | | E.g. we print "ldr x0, [x0, :lo12:symbol]" so we need to accept that syntax too. llvm-svn: 207639
* ARM64: remove duplication by templating InstPrinter methodsTim Northover2014-04-304-215/+65
| | | | | | No functional change, so no tests. llvm-svn: 207638
* ARM64: use hex immediates for movz/movk instructionsTim Northover2014-04-301-0/+1
| | | | | | | | Since these are mostly used in "lsl #16", "lsl #32", "lsl #48" combinations to piece together an immediate in 16-bit chunks, hex is probably the most appropriate format. llvm-svn: 207635
* ARM64: hexify printing various immediate operandsTim Northover2014-04-303-0/+10
| | | | | | | | | | This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. llvm-svn: 207634
* ARM64: print canonical syntax for add/sub (imm) instructions.Tim Northover2014-04-301-3/+5
| | | | | | | | | | Since these instructions only accept a 12-bit immediate, possibly shifted left by 12, the canonical syntax used by the architecture reference manual is "#N {, lsl #12 }". We should accept an immediate that has already been shifted, (e.g. Also, print a comment giving the full addend since it can be helpful. llvm-svn: 207633
* [ARM64] Simplify if condition.James Molloy2014-04-301-6/+2
| | | | | | | v2f32 and v4f32 were missed out of these conditions, so this is also a bugfix. llvm-svn: 207628
* [ARM64] Fix stupid copy-pasto in ARM64MCAsmInfo.cpp - aarch64_be -> arm64_beJames Molloy2014-04-301-1/+1
| | | | llvm-svn: 207627
* ARM64: make sure FastISel uses a GPR64 source in 64-bit extensions.Tim Northover2014-04-301-0/+9
| | | | llvm-svn: 207620
* Use makeArrayRef insted of calling ArrayRef<T> constructor directly. I ↵Craig Topper2014-04-301-3/+3
| | | | | | introduced most of these recently. llvm-svn: 207616
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-2927-132/+141
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. ARM64 edition llvm-svn: 207509
* [ARM64]Fix a bug about incorrect operand order in an EXT instruction, which ↵Hao Liu2014-04-291-3/+9
| | | | | | is introduced by r207485. llvm-svn: 207500
* [ARM64]Fix a bug when lowering shuffle vector to an EXT instruction.Hao Liu2014-04-291-28/+23
| | | | | | E.g. Mask like <-1, -1, 1, ...> will generate incorrect EXT index. llvm-svn: 207485
* [ARM64] Fix an issue where we were always assuming a copy was coming from a ↵Chad Rosier2014-04-281-3/+3
| | | | | | D subregister. llvm-svn: 207423
* ARM64: diagnose use of v16-v31 in certain indexed NEON instructions.Tim Northover2014-04-282-1/+14
| | | | | | | | | | | Someone couldn't bear to have a completely orthogonal set of floating-point registers, so we've got some instructions that only accept v0-v15 (coming in ARMv9, V128_prime: you're allowed v2, v3, v5, v7, ...). Anyway, we were permitting even the out of range registers during assembly (CodeGen handled it correctly). This adds a diagnostic. llvm-svn: 207412
* [ARM64]Fix a bug cannot select UQSHL/SQSHL with constant i64 shift amount.Hao Liu2014-04-281-2/+4
| | | | llvm-svn: 207399
* [C++] Use 'nullptr'.Craig Topper2014-04-284-8/+8
| | | | llvm-svn: 207394
* Convert SelectionDAG::SelectNodeTo to use ArrayRef.Craig Topper2014-04-271-3/+3
| | | | llvm-svn: 207377
* Convert SelectionDAG::getMergeValues to use ArrayRef.Craig Topper2014-04-271-3/+3
| | | | llvm-svn: 207374
* Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>.Craig Topper2014-04-261-19/+16
| | | | llvm-svn: 207327
* DAGCombiner: Turn divs of vector splats into vectorized multiplications.Benjamin Kramer2014-04-261-0/+5
| | | | | | | | | | | | Otherwise the legalizer would just scalarize everything. Support for mulhi in the targets isn't that great yet so on most targets we get exactly the same scalarized output. Add a test for x86 vector udiv. I had to disable the mulhi nodes on ARM because there aren't any patterns for it. As far as I know ARM has instructions for getting the high part of a multiply so this should be fixed. llvm-svn: 207315
* Revert r206749 till a final decision about the intrinsics is made.Michael Zolotukhin2014-04-261-2/+0
| | | | llvm-svn: 207313
* [ARM64] When compiling for ELF in PIC mode, local symbols shouldn't go ↵Tilmann Scheller2014-04-251-1/+2
| | | | | | | | | | | | through the GOT There's no need for local symbols to go through the GOT, in fact it seems GNU ld is not even emitting GOT entries for local symbols and will error out when trying to resolve a GOT relocation for a local symbol. This bug triggers when bootstrapping clang on AArch64 Linux with -fPIC and the ARM64 backend. The AArch64 backend is not affected. With this commit it's now possible to bootstrap clang on AArch64 Linux with the ARM64 backend (-fPIC, -O3). llvm-svn: 207226
* [ARM64] Handle fp128 for parameter passing on stackJiangning Liu2014-04-251-1/+2
| | | | llvm-svn: 207222
* ARM64: fix assertion in ISelDAGToDAGTim Northover2014-04-251-2/+0
| | | | | | | | Also an unused variable, so double bonus! This should deal with PR19548. llvm-svn: 207221
* [ARM64] Print preferred aliases for SFBM/UBFM in InstPrinterBradley Smith2014-04-251-6/+29
| | | | llvm-svn: 207219
* [ARM64] Add RUN lines for "–target arm64 –mattr=-fp-armv8" on AArch64 ↵Kevin Qin2014-04-251-3/+3
| | | | | | | | | | no-fp test. This patch is a supplement of implementing predicate of FP, enabling aarch64 backend no-fp tests on arm64 target for verification. During this, one bug is exposed and fixed by this patch. llvm-svn: 207215
* [ARM64] Support crc predicate on ARM64.Kevin Qin2014-04-255-5/+18
| | | | | | | According to the specification, CRC is an optional extension of the architecture. llvm-svn: 207214
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-2518-86/+86
| | | | llvm-svn: 207197
* Add 'musttail' marker to call instructionsReid Kleckner2014-04-241-0/+3
| | | | | | | | | | | | This is similar to the 'tail' marker, except that it guarantees that tail call optimization will occur. It also comes with convervative IR verification rules that ensure that tail call optimization is possible. Reviewers: nicholas Differential Revision: http://llvm-reviews.chandlerc.com/D3240 llvm-svn: 207143
* Spread some const around for non-mutating uses of MCSymbolData.David Blaikie2014-04-241-3/+3
| | | | | | | | I discovered this const-hole while attempting to coalesnce the Symbol and SymbolMap data structures. There's some pending issues with that, but I figured this change was easy to flush early. llvm-svn: 207124
* AArch64/ARM64: allow negative addends, at least on ELF.Tim Northover2014-04-241-14/+18
| | | | llvm-svn: 207111
* ARM64: support relocated "TBZ/TBNZ" instructions.Tim Northover2014-04-241-0/+2
| | | | llvm-svn: 207110
* AArch64/ARM64: support relocated ADR instructionTim Northover2014-04-241-1/+2
| | | | llvm-svn: 207109
* AArch64/ARM64: add support for :abs_gN_s: MOVZ modifiersTim Northover2014-04-246-0/+33
| | | | | | We only need assembly support, so it's fairly easy. llvm-svn: 207108
* ARM64: shut up warning about variable only used in assert.Tim Northover2014-04-241-0/+1
| | | | llvm-svn: 207106
* AArch64/ARM64: disentangle the "B.CC" and "LDR lit" operandsTim Northover2014-04-2410-37/+77
| | | | | | | | | | | | | These can have different relocations in ELF. In particular both: b.eq global ldr x0, global are valid, giving different relocations. The only possible way to distinguish them is via a different fixup, so the operands had to be separated throughout the backend. llvm-svn: 207105
* AArch64/ARM64: implement BFI optimisationTim Northover2014-04-241-45/+122
| | | | | | | | | | | ARM64 was not producing pure BFI instructions for bitfield insertion operations, unlike AArch64. The approach had to be a little different (in ISelDAGToDAG rather than ISelLowering), and the outcomes aren't identical but hopefully this gives it similar power. This should address PR19424. llvm-svn: 207102
* [ARM64] Fix the information we give to the peephole optimizer for comparison.Quentin Colombet2014-04-231-2/+11
| | | | | | | | | ANDS does not use the same encoding scheme as other xxxS instructions (e.g., ADDS). Take that into account to avoid wrong peephole optimization. <rdar://problem/16693089> llvm-svn: 207020
* Create MCTargetOptions.Evgeniy Stepanov2014-04-231-1/+2
| | | | | | | | | For now it contains a single flag, SanitizeAddress, which enables AddressSanitizer instrumentation of inline assembly. Patch by Yuri Gorshenin. llvm-svn: 206971
* [ARM64] Fix formatting.James Molloy2014-04-231-1/+1
| | | | llvm-svn: 206967
* [ARM64] Add a big endian version of the ARM64 target machine, and update all ↵James Molloy2014-04-2314-44/+139
| | | | | | | | users. This completes the porting of r202024 (cpirker "Add AArch64 big endian Target (aarch64_be)") to ARM64. llvm-svn: 206965
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