summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM64
Commit message (Collapse)AuthorAgeFilesLines
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-2927-132/+141
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. ARM64 edition llvm-svn: 207509
* [ARM64]Fix a bug about incorrect operand order in an EXT instruction, which ↵Hao Liu2014-04-291-3/+9
| | | | | | is introduced by r207485. llvm-svn: 207500
* [ARM64]Fix a bug when lowering shuffle vector to an EXT instruction.Hao Liu2014-04-291-28/+23
| | | | | | E.g. Mask like <-1, -1, 1, ...> will generate incorrect EXT index. llvm-svn: 207485
* [ARM64] Fix an issue where we were always assuming a copy was coming from a ↵Chad Rosier2014-04-281-3/+3
| | | | | | D subregister. llvm-svn: 207423
* ARM64: diagnose use of v16-v31 in certain indexed NEON instructions.Tim Northover2014-04-282-1/+14
| | | | | | | | | | | Someone couldn't bear to have a completely orthogonal set of floating-point registers, so we've got some instructions that only accept v0-v15 (coming in ARMv9, V128_prime: you're allowed v2, v3, v5, v7, ...). Anyway, we were permitting even the out of range registers during assembly (CodeGen handled it correctly). This adds a diagnostic. llvm-svn: 207412
* [ARM64]Fix a bug cannot select UQSHL/SQSHL with constant i64 shift amount.Hao Liu2014-04-281-2/+4
| | | | llvm-svn: 207399
* [C++] Use 'nullptr'.Craig Topper2014-04-284-8/+8
| | | | llvm-svn: 207394
* Convert SelectionDAG::SelectNodeTo to use ArrayRef.Craig Topper2014-04-271-3/+3
| | | | llvm-svn: 207377
* Convert SelectionDAG::getMergeValues to use ArrayRef.Craig Topper2014-04-271-3/+3
| | | | llvm-svn: 207374
* Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>.Craig Topper2014-04-261-19/+16
| | | | llvm-svn: 207327
* DAGCombiner: Turn divs of vector splats into vectorized multiplications.Benjamin Kramer2014-04-261-0/+5
| | | | | | | | | | | | Otherwise the legalizer would just scalarize everything. Support for mulhi in the targets isn't that great yet so on most targets we get exactly the same scalarized output. Add a test for x86 vector udiv. I had to disable the mulhi nodes on ARM because there aren't any patterns for it. As far as I know ARM has instructions for getting the high part of a multiply so this should be fixed. llvm-svn: 207315
* Revert r206749 till a final decision about the intrinsics is made.Michael Zolotukhin2014-04-261-2/+0
| | | | llvm-svn: 207313
* [ARM64] When compiling for ELF in PIC mode, local symbols shouldn't go ↵Tilmann Scheller2014-04-251-1/+2
| | | | | | | | | | | | through the GOT There's no need for local symbols to go through the GOT, in fact it seems GNU ld is not even emitting GOT entries for local symbols and will error out when trying to resolve a GOT relocation for a local symbol. This bug triggers when bootstrapping clang on AArch64 Linux with -fPIC and the ARM64 backend. The AArch64 backend is not affected. With this commit it's now possible to bootstrap clang on AArch64 Linux with the ARM64 backend (-fPIC, -O3). llvm-svn: 207226
* [ARM64] Handle fp128 for parameter passing on stackJiangning Liu2014-04-251-1/+2
| | | | llvm-svn: 207222
* ARM64: fix assertion in ISelDAGToDAGTim Northover2014-04-251-2/+0
| | | | | | | | Also an unused variable, so double bonus! This should deal with PR19548. llvm-svn: 207221
* [ARM64] Print preferred aliases for SFBM/UBFM in InstPrinterBradley Smith2014-04-251-6/+29
| | | | llvm-svn: 207219
* [ARM64] Add RUN lines for "–target arm64 –mattr=-fp-armv8" on AArch64 ↵Kevin Qin2014-04-251-3/+3
| | | | | | | | | | no-fp test. This patch is a supplement of implementing predicate of FP, enabling aarch64 backend no-fp tests on arm64 target for verification. During this, one bug is exposed and fixed by this patch. llvm-svn: 207215
* [ARM64] Support crc predicate on ARM64.Kevin Qin2014-04-255-5/+18
| | | | | | | According to the specification, CRC is an optional extension of the architecture. llvm-svn: 207214
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-2518-86/+86
| | | | llvm-svn: 207197
* Add 'musttail' marker to call instructionsReid Kleckner2014-04-241-0/+3
| | | | | | | | | | | | This is similar to the 'tail' marker, except that it guarantees that tail call optimization will occur. It also comes with convervative IR verification rules that ensure that tail call optimization is possible. Reviewers: nicholas Differential Revision: http://llvm-reviews.chandlerc.com/D3240 llvm-svn: 207143
* Spread some const around for non-mutating uses of MCSymbolData.David Blaikie2014-04-241-3/+3
| | | | | | | | I discovered this const-hole while attempting to coalesnce the Symbol and SymbolMap data structures. There's some pending issues with that, but I figured this change was easy to flush early. llvm-svn: 207124
* AArch64/ARM64: allow negative addends, at least on ELF.Tim Northover2014-04-241-14/+18
| | | | llvm-svn: 207111
* ARM64: support relocated "TBZ/TBNZ" instructions.Tim Northover2014-04-241-0/+2
| | | | llvm-svn: 207110
* AArch64/ARM64: support relocated ADR instructionTim Northover2014-04-241-1/+2
| | | | llvm-svn: 207109
* AArch64/ARM64: add support for :abs_gN_s: MOVZ modifiersTim Northover2014-04-246-0/+33
| | | | | | We only need assembly support, so it's fairly easy. llvm-svn: 207108
* ARM64: shut up warning about variable only used in assert.Tim Northover2014-04-241-0/+1
| | | | llvm-svn: 207106
* AArch64/ARM64: disentangle the "B.CC" and "LDR lit" operandsTim Northover2014-04-2410-37/+77
| | | | | | | | | | | | | These can have different relocations in ELF. In particular both: b.eq global ldr x0, global are valid, giving different relocations. The only possible way to distinguish them is via a different fixup, so the operands had to be separated throughout the backend. llvm-svn: 207105
* AArch64/ARM64: implement BFI optimisationTim Northover2014-04-241-45/+122
| | | | | | | | | | | ARM64 was not producing pure BFI instructions for bitfield insertion operations, unlike AArch64. The approach had to be a little different (in ISelDAGToDAG rather than ISelLowering), and the outcomes aren't identical but hopefully this gives it similar power. This should address PR19424. llvm-svn: 207102
* [ARM64] Fix the information we give to the peephole optimizer for comparison.Quentin Colombet2014-04-231-2/+11
| | | | | | | | | ANDS does not use the same encoding scheme as other xxxS instructions (e.g., ADDS). Take that into account to avoid wrong peephole optimization. <rdar://problem/16693089> llvm-svn: 207020
* Create MCTargetOptions.Evgeniy Stepanov2014-04-231-1/+2
| | | | | | | | | For now it contains a single flag, SanitizeAddress, which enables AddressSanitizer instrumentation of inline assembly. Patch by Yuri Gorshenin. llvm-svn: 206971
* [ARM64] Fix formatting.James Molloy2014-04-231-1/+1
| | | | llvm-svn: 206967
* [ARM64] Add a big endian version of the ARM64 target machine, and update all ↵James Molloy2014-04-2314-44/+139
| | | | | | | | users. This completes the porting of r202024 (cpirker "Add AArch64 big endian Target (aarch64_be)") to ARM64. llvm-svn: 206965
* [ARM64] Enable feature predicates for NEON / FP / CRYPTO.Kevin Qin2014-04-238-188/+330
| | | | | | | | AArch64 has feature predicates for NEON, FP and CRYPTO instructions. This allows the compiler to generate code without using FP, NEON or CRYPTO instructions. llvm-svn: 206949
* Fix the assembler to print a better relocatable expression errorKevin Enderby2014-04-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | diagnostic that includes location information. Currently if one has this assembly: .quad (0x1234 + (4 * SOME_VALUE)) where SOME_VALUE is undefined ones gets the less than useful error message with no location information: % clang -c x.s clang -cc1as: fatal error: error in backend: expected relocatable expression With this fix one now gets a more useful error message with location information: % clang -c x.s x.s:5:8: error: expected relocatable expression .quad (0x1234 + (4 * SOME_VALUE)) ^ To do this I plumbed the SMLoc through the MCObjectStreamer EmitValue() and EmitValueImpl() interfaces so it could be used when creating the MCFixup. rdar://12391022 llvm-svn: 206906
* AArch64/ARM64: make use of ANDS and BICS instructions for comparisons.Tim Northover2014-04-224-17/+42
| | | | llvm-svn: 206888
* AArch64/ARM64: add patterns for scalar_to_vector/extract pairsTim Northover2014-04-221-0/+4
| | | | llvm-svn: 206876
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-2220-23/+40
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* [cleanup] Lift using directives, DEBUG_TYPE definitions, and even someChandler Carruth2014-04-225-10/+10
| | | | | | | | | | | | system headers above the includes of generated '.inc' files that actually contain code. In a few targets this was already done pretty consistently, but it wasn't done *really* consistently anywhere. It is strictly cleaner IMO and necessary in a bunch of places where the DEBUG_TYPE is referenced from the generated code. Consistency with the necessary places trumps. Hopefully the build bots are OK with the movement of intrin.h... llvm-svn: 206838
* [Modules] Make Support/Debug.h modular. This requires it to not changeChandler Carruth2014-04-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | behavior based on other files defining DEBUG_TYPE, which means it cannot define DEBUG_TYPE at all. This is actually better IMO as it forces folks to define relevant DEBUG_TYPEs for their files. However, it requires all files that currently use DEBUG(...) to define a DEBUG_TYPE if they don't already. I've updated all such files in LLVM and will do the same for other upstream projects. This still leaves one important change in how LLVM uses the DEBUG_TYPE macro going forward: we need to only define the macro *after* header files have been #include-ed. Previously, this wasn't possible because Debug.h required the macro to be pre-defined. This commit removes that. By defining DEBUG_TYPE after the includes two things are fixed: - Header files that need to provide a DEBUG_TYPE for some inline code can do so by defining the macro before their inline code and undef-ing it afterward so the macro does not escape. - We no longer have rampant ODR violations due to including headers with different DEBUG_TYPE definitions. This may be mostly an academic violation today, but with modules these types of violations are easy to check for and potentially very relevant. Where necessary to suppor headers with DEBUG_TYPE, I have moved the definitions below the includes in this commit. I plan to move the rest of the DEBUG_TYPE macros in LLVM in subsequent commits; this one is big enough. The comments in Debug.h, which were hilariously out of date already, have been updated to reflect the recommended practice going forward. llvm-svn: 206822
* ARM64: Refactor away a few redundant helpers.Jim Grosbach2014-04-211-66/+33
| | | | | | | | | The comment claimed that the register class information wasn't available in the assembly parser, but that's not really true. It's just annoying to get to. Replace the helper functions with references to the auto-generated information. llvm-svn: 206802
* ARM64: Improve diagnostics for malformed reg+reg addressing mode.Jim Grosbach2014-04-211-1/+12
| | | | | | | Make sure only general purpose registers are valid for offset regs and that 32-bit regs are only valid for sxtw and uxtw extends. llvm-svn: 206799
* Move helper functions earlier in the file.Jim Grosbach2014-04-211-54/+53
| | | | | | No functional change. llvm-svn: 206798
* ARM64: Extended addressing mode source reg is 64-bit.Jim Grosbach2014-04-211-5/+1
| | | | | | | | | | | | | | The canonical form for the extended addressing mode (e.g., "[x1, w2, uxtw #3]" is for the MCInst to have the second register be the full 64-bit GPR64 register class. The instruction printer cleans up the output for display to show the 32-bit register instead, per the specification. This simplifies 205893 now that the aliasing is handled in the printer in 206495 so that the codegen path and the disassembler path give the same MCInst form. llvm-svn: 206797
* ARM64: Combine shifts and uses from different basic block to bit-extract ↵Yi Jiang2014-04-212-3/+39
| | | | | | instruction llvm-svn: 206774
* Reapply r206732. This time without optimization of branches.Michael Zolotukhin2014-04-211-0/+2
| | | | llvm-svn: 206749
* Revert r206732 which is causing llc to crash on most of the build bots.Chandler Carruth2014-04-211-2/+0
| | | | | | | | Original commit message: Implement builtins for safe division: safe.sdiv.iN, safe.udiv.iN, safe.srem.iN, safe.urem.iN (iN = i8, i61, i32, or i64). llvm-svn: 206735
* Implement builtins for safe division: safe.sdiv.iN, safe.udiv.iN, safe.srem.iN,Michael Zolotukhin2014-04-211-0/+2
| | | | | | safe.urem.iN (iN = i8, i16, i32, or i64). llvm-svn: 206732
* [ARM64] Ports the Cortex-A53 Machine Model description from AArch64.Chad Rosier2014-04-183-4/+135
| | | | | | | | | | | | | Summary: This port includes the rudimentary latencies that were provided for the Cortex-A53 Machine Model in the AArch64 backend. It also changes the SchedAlias for COPY in the Cyclone model to an explicit WriteRes mapping to avoid conflicts in other subtargets. Differential Revision: http://reviews.llvm.org/D3427 Patch by Dave Estes <cestes@codeaurora.org>! llvm-svn: 206652
* ARM64: disable generation of .loh directives outside MachO.Tim Northover2014-04-181-1/+2
| | | | | | Part of PR19455. llvm-svn: 206611
* ARM64: don't emit .subsections_via_symbols on ELF.Tim Northover2014-04-181-7/+9
| | | | | | Part of PR19455. llvm-svn: 206610
OpenPOWER on IntegriCloud