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* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-244-4074/+0
| | | | | | | | | | | | | | | This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
* AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.Tim Northover2014-05-241-0/+3
| | | | | | | | | | | | | | | | I'm doing this in two phases for a better "git blame" record. This commit removes the previous AArch64 backend and redirects all functionality to ARM64. It also deduplicates test-lines and removes orphaned AArch64 tests. The next step will be "git mv ARM64 AArch64" and rewire most of the tests. Hopefully LLVM is still functional, though it would be even better if no-one ever had to care because the rename happens straight afterwards. llvm-svn: 209576
* ARM64: model pre/post-indexed operations properly.Tim Northover2014-05-221-17/+23
| | | | | | | | | | We should be keeping track of the writeback on these instructions, otherwise we're relying on LLVM's stupidity for correct code. Fortunately, the MC layer can now handle all required constraints, which means we can get rid of the CodeGen only PseudoInsts too. llvm-svn: 209426
* ARM64: separate load/store operands to simplify assemblerTim Northover2014-05-221-662/+253
| | | | | | | | | | | | | | | | | | | This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
* [ARM64] Split tbz/tbnz into W/X register variantBradley Smith2014-05-191-21/+31
| | | | llvm-svn: 209134
* [ARM64] Improve diagnostics for Cn operands in SYS instructionsBradley Smith2014-05-151-69/+24
| | | | llvm-svn: 208902
* ARM64: add correct vector registers during asm parsingTim Northover2014-05-151-1/+8
| | | | | | | | | Previously, we ignored the difference between V64 and V128 when parsing assembly: they both got mapped to registers in the FPR128 class. This is basically harmless at the moment because they both print and encode the same way. However, it will affect the printing of aliases. llvm-svn: 208866
* [ARM64] Improve load/store diagnostics and forbid 32-bit register addressesBradley Smith2014-05-151-2/+11
| | | | llvm-svn: 208864
* [ARM64] Parse fixed vector lanes properly so that diagnostics can be emittedBradley Smith2014-05-151-39/+11
| | | | llvm-svn: 208863
* [ARM64] Add/Fixup diagnostics for floating point immediatesBradley Smith2014-05-151-3/+17
| | | | llvm-svn: 208862
* [ARM64] Add condition code operand type such that proper diagnostics can be ↵Bradley Smith2014-05-151-9/+44
| | | | | | emitted llvm-svn: 208861
* [ARM64] Add more simple diagnostics for immediate/shift rangesBradley Smith2014-05-151-0/+12
| | | | llvm-svn: 208860
* [ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg ↵Kevin Qin2014-05-131-11/+7
| | | | | | | | | addressing mode. A vague diagnostic replaced the misleading one. This can fix bug 19502. llvm-svn: 208669
* AArch64/ARM64: use InstAliases for NEON logical (imm) instructions.Tim Northover2014-05-121-72/+26
| | | | llvm-svn: 208606
* AArch64/ARM64: implement "mov $Rd, $Imm" aliases in TableGen.Tim Northover2014-05-121-58/+57
| | | | | | | | This is a slightly different approach to AArch64 (the base instruction definitions aren't quite right for that to work), but achieves the same thing and reduces C++ hackery in AsmParser. llvm-svn: 208605
* ARM64: remove dead validation code from the AsmParser.Tim Northover2014-05-121-198/+0
| | | | | | | If this code triggers, any immediate has already been validated so it can't possibly trigger a diagnostic. llvm-svn: 208564
* ARM64: merge "extend" and "shift" addressing-mode enums.Tim Northover2014-05-121-251/+118
| | | | | | | | In terms of assembly, these have too much overlap to be neatly modelled as disjoint classes: in many cases "lsl" is an acceptable alternative to either "uxtw" or "uxtx". llvm-svn: 208563
* [ARM64] Add proper bounds checking/diagnostics to logical shiftsBradley Smith2014-05-121-12/+17
| | | | llvm-svn: 208540
* [ARM64] Add diagnostics for bitfield extract/insert instructionsBradley Smith2014-05-121-19/+54
| | | | | | | | Unfortunately, since ARM64 models all these instructions as aliases, the checks need to be done at the time the alias is seen rather than during instruction validation as AArch64 does it. llvm-svn: 208529
* [ARM64] Correct more bounds checks/diagnostics for arithmetic shift operandsBradley Smith2014-05-121-9/+17
| | | | llvm-svn: 208528
* [ARM64] Move register/register MOV handling into tablegen and improve ↵Bradley Smith2014-05-121-52/+3
| | | | | | diagnostics llvm-svn: 208527
* [ARM64] Add diagnostics for expected arithmetic shiftsBradley Smith2014-05-081-0/+8
| | | | llvm-svn: 208330
* [ARM64] Re-work parsing of ADD/SUB shifted immediate operandsBradley Smith2014-05-081-115/+175
| | | | | | | | | | | | The parsing of ADD/SUB shifted immediates needs to be done explicitly so that better diagnostics can be emitted, as a side effect this also removes some of the hacks in the current method of handling this operand type. Additionally remove manual CMP aliasing to ADD/SUB and use InstAlias instead. llvm-svn: 208329
* [ARM64] Ensure immediates in extend operands are in a valid rangeBradley Smith2014-05-081-3/+13
| | | | | | Also emit a more useful diagnostic when they are not. llvm-svn: 208318
* [ARM64] Check for proper immediate in shift/extend operandsBradley Smith2014-05-081-42/+58
| | | | llvm-svn: 208317
* AArch64/ARM64: make NEON vector list parsing a bit more robustTim Northover2014-05-061-2/+5
| | | | | | | It doesn't change the results, but it seems silly not to diagnose obvious problems early on. llvm-svn: 208083
* AArch64/ARM64: add more specific diagnostic for floating imm 0.0.Tim Northover2014-05-061-4/+5
| | | | llvm-svn: 208082
* AArch64/ARM64: add more specific diagnostic for invalid vector lanesTim Northover2014-05-061-0/+12
| | | | llvm-svn: 208081
* AArch64/ARM64: produce more informative diagnostic assembling some immediatesTim Northover2014-05-061-13/+25
| | | | | | | No tests here, they'll be added when the entire neon-diagnostics.s test from AArch64 is enabled. llvm-svn: 208079
* [ARM64] Conditionalize CPU specific system registers on subtarget featuresBradley Smith2014-05-011-6/+20
| | | | llvm-svn: 207742
* AArch64/ARM64: implement remaining TLS relocations (purely MC).Tim Northover2014-04-301-8/+16
| | | | llvm-svn: 207668
* AArch64/ARM64: add specific diagnostic for MRS/MSR and enable tests.Tim Northover2014-04-301-1/+7
| | | | llvm-svn: 207667
* AArch64/ARM64: accept and print floating-point immediate 0 as "#0.0"Tim Northover2014-04-301-1/+4
| | | | | | | | | | It's been decided that in the future, the floating-point immediate in instructions like "fcmeq v0.2s, v1.2s, #0.0" will be canonically "0.0", which has been implemented on AArch64 already but not ARM64. This fixes that issue. llvm-svn: 207666
* ARM64: use 32-bit operations for uxtb & uxthTim Northover2014-04-301-3/+19
| | | | | | Testing will be enabled shortly with basic-a64-instructions.s llvm-svn: 207648
* AArch64/ARM64: copy support for bCC instead of b.CC across.Tim Northover2014-04-301-0/+21
| | | | llvm-svn: 207646
* AArch64/ARM64: expunge CPSR from the sourcesTim Northover2014-04-301-2/+2
| | | | | | | | | | | | AArch64 does not have a CPSR register in the same way that AArch32 does. Most of its compiler-relevant roles have been taken over by the more specific NZCV register (representing just the flags set by normal instructions). Its system control functions still remain, but are now under the pseudo-register referred to as "PSTATE". They're accessed via various MRS & MSR instructions described in the reference manual. llvm-svn: 207645
* AArch64/ARM64: use HS instead of CS & LO instead of CC.Tim Northover2014-04-301-4/+4
| | | | | | | | | On instructions using the NZCV register, a couple of conditions have dual representations: HS/CS and LO/CC (meaning unsigned-higher-or-same/carry-set and unsigned-lower/carry-clear). The first of these is more descriptive in most circumstances, so we should print it. llvm-svn: 207644
* ARM64: accept ELF-relocated load/store insts without a #.Tim Northover2014-04-301-0/+1
| | | | | | | E.g. we print "ldr x0, [x0, :lo12:symbol]" so we need to accept that syntax too. llvm-svn: 207639
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-14/+16
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. ARM64 edition llvm-svn: 207509
* ARM64: diagnose use of v16-v31 in certain indexed NEON instructions.Tim Northover2014-04-281-0/+9
| | | | | | | | | | | Someone couldn't bear to have a completely orthogonal set of floating-point registers, so we've got some instructions that only accept v0-v15 (coming in ARMv9, V128_prime: you're allowed v2, v3, v5, v7, ...). Anyway, we were permitting even the out of range registers during assembly (CodeGen handled it correctly). This adds a diagnostic. llvm-svn: 207412
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-7/+7
| | | | llvm-svn: 207197
* AArch64/ARM64: allow negative addends, at least on ELF.Tim Northover2014-04-241-14/+18
| | | | llvm-svn: 207111
* AArch64/ARM64: add support for :abs_gN_s: MOVZ modifiersTim Northover2014-04-241-0/+11
| | | | | | We only need assembly support, so it's fairly easy. llvm-svn: 207108
* AArch64/ARM64: disentangle the "B.CC" and "LDR lit" operandsTim Northover2014-04-241-2/+2
| | | | | | | | | | | | | These can have different relocations in ELF. In particular both: b.eq global ldr x0, global are valid, giving different relocations. The only possible way to distinguish them is via a different fixup, so the operands had to be separated throughout the backend. llvm-svn: 207105
* Create MCTargetOptions.Evgeniy Stepanov2014-04-231-1/+2
| | | | | | | | | For now it contains a single flag, SanitizeAddress, which enables AddressSanitizer instrumentation of inline assembly. Patch by Yuri Gorshenin. llvm-svn: 206971
* [ARM64] Add a big endian version of the ARM64 target machine, and update all ↵James Molloy2014-04-231-1/+2
| | | | | | | | users. This completes the porting of r202024 (cpirker "Add AArch64 big endian Target (aarch64_be)") to ARM64. llvm-svn: 206965
* [ARM64] Enable feature predicates for NEON / FP / CRYPTO.Kevin Qin2014-04-231-1/+21
| | | | | | | | AArch64 has feature predicates for NEON, FP and CRYPTO instructions. This allows the compiler to generate code without using FP, NEON or CRYPTO instructions. llvm-svn: 206949
* ARM64: Refactor away a few redundant helpers.Jim Grosbach2014-04-211-66/+33
| | | | | | | | | The comment claimed that the register class information wasn't available in the assembly parser, but that's not really true. It's just annoying to get to. Replace the helper functions with references to the auto-generated information. llvm-svn: 206802
* ARM64: Improve diagnostics for malformed reg+reg addressing mode.Jim Grosbach2014-04-211-1/+12
| | | | | | | Make sure only general purpose registers are valid for offset regs and that 32-bit regs are only valid for sxtw and uxtw extends. llvm-svn: 206799
* Move helper functions earlier in the file.Jim Grosbach2014-04-211-54/+53
| | | | | | No functional change. llvm-svn: 206798
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