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path: root/llvm/lib/Target/ARM64/ARM64TargetMachine.cpp
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* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-208/+0
| | | | | | | | | | | | | | | This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
* AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.Tim Northover2014-05-241-0/+3
| | | | | | | | | | | | | | | | I'm doing this in two phases for a better "git blame" record. This commit removes the previous AArch64 backend and redirects all functionality to ARM64. It also deduplicates test-lines and removes orphaned AArch64 tests. The next step will be "git mv ARM64 AArch64" and rewire most of the tests. Hopefully LLVM is still functional, though it would be even better if no-one ever had to care because the rename happens straight afterwards. llvm-svn: 209576
* Make early if conversion dependent upon the subtarget and addEric Christopher2014-05-211-6/+1
| | | | | | | a subtarget hook to enable. Unconditionally add to the pass pipeline for targets that might want to use it. No functional change. llvm-svn: 209340
* [ARM64][fast-isel] Disable target specific optimizations at -O0. Functionally,Chad Rosier2014-05-071-17/+30
| | | | | | | | | | | | | | | this patch disables the dead register elimination pass and the load/store pair optimization pass at -O0. The ILP optimizations don't require the optimization level to be checked because the call to addILPOpts is predicated with the necessary check. The AdvSIMDScalar pass is disabled by default at all optimization levels. This patch leaves that pass disabled by default. Also, move command-line options into ARM64TargetMachine.cpp and add a few additional flags to aid in debugging. This fixes an issue with the -debug-pass=Structure flag where passes were printed, but not actually run (i.e., AdvSIMDScalar pass). llvm-svn: 208223
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-7/+7
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. ARM64 edition llvm-svn: 207509
* [ARM64] Add a big endian version of the ARM64 target machine, and update all ↵James Molloy2014-04-231-5/+30
| | | | | | | | users. This completes the porting of r202024 (cpirker "Add AArch64 big endian Target (aarch64_be)") to ARM64. llvm-svn: 206965
* ARM64: disable generation of .loh directives outside MachO.Tim Northover2014-04-181-1/+2
| | | | | | Part of PR19455. llvm-svn: 206611
* ARM64: add acquire/release versions of the existing atomic intrinsics.Tim Northover2014-04-171-0/+5
| | | | | | | These will be needed to support IR-level lowering of atomic operations. llvm-svn: 206489
* Add a flag to disable the ARM64DeadRegisterDefinitionsPassLouis Gerbarg2014-04-141-1/+10
| | | | | | | This patch adds a -arm64-dead-def-elimination flag so that it is possible to disable dead definition elimination. Includes test case. llvm-svn: 206207
* ARM64: initial backend importTim Northover2014-03-291-0/+157
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
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