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* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-3030/+0
| | | | | | | | | | | | | | | This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
* ARM64: extract a 32-bit subreg when selecting an inreg extendTim Northover2014-05-241-10/+19
| | | | | | | | After the load/store refactoring, we were sometimes trying to feed a GPR64 into a 32-bit register offset operand. This failed in copyPhysReg. llvm-svn: 209566
* ARM64: model pre/post-indexed operations properly.Tim Northover2014-05-221-22/+26
| | | | | | | | | | We should be keeping track of the writeback on these instructions, otherwise we're relying on LLVM's stupidity for correct code. Fortunately, the MC layer can now handle all required constraints, which means we can get rid of the CodeGen only PseudoInsts too. llvm-svn: 209426
* ARM64: separate load/store operands to simplify assemblerTim Northover2014-05-221-73/+104
| | | | | | | | | | | | | | | | | | | This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
* ARM64: assert if we see i64 -> i64 extend in the DAG.Tim Northover2014-05-221-4/+2
| | | | | | | | Should be no change in behaviour, but it makes the intended functionality a bit clearer and means we only have to reason about real extend operations. llvm-svn: 209409
* Reset the subtarget for DAGToDAG on every iteration of runOnMachineFunction.Eric Christopher2014-05-221-1/+2
| | | | llvm-svn: 209374
* [ARM64]Implement NEON post-increment LD1(lane) and post-increment LD1R.Hao Liu2014-05-161-11/+52
| | | | llvm-svn: 208955
* Rename ComputeMaskedBits to computeKnownBits. "Masked" has beenJay Foad2014-05-141-3/+3
| | | | | | inappropriate since it lost its Mask parameter in r154011. llvm-svn: 208811
* ARM64: merge "extend" and "shift" addressing-mode enums.Tim Northover2014-05-121-21/+21
| | | | | | | | In terms of assembly, these have too much overlap to be neatly modelled as disjoint classes: in many cases "lsl" is an acceptable alternative to either "uxtw" or "uxtx". llvm-svn: 208563
* AArch64/ARM64: Port NEON post-increment load/store with 2/3/4 vectors to ↵Hao Liu2014-05-081-55/+529
| | | | | | ARM64 backend. llvm-svn: 208284
* AArch64/ARM64: support indexed loads/stores on vector types.Tim Northover2014-05-021-1/+3
| | | | | | | | While post-indexed LD1/ST1 instructions do exist for vector loads, this patch makes use of the more flexible addressing-modes in LDR/STR instructions. llvm-svn: 207838
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-6/+6
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. ARM64 edition llvm-svn: 207509
* Convert SelectionDAG::SelectNodeTo to use ArrayRef.Craig Topper2014-04-271-3/+3
| | | | llvm-svn: 207377
* ARM64: fix assertion in ISelDAGToDAGTim Northover2014-04-251-2/+0
| | | | | | | | Also an unused variable, so double bonus! This should deal with PR19548. llvm-svn: 207221
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-14/+14
| | | | llvm-svn: 207197
* ARM64: shut up warning about variable only used in assert.Tim Northover2014-04-241-0/+1
| | | | llvm-svn: 207106
* AArch64/ARM64: implement BFI optimisationTim Northover2014-04-241-45/+122
| | | | | | | | | | | ARM64 was not producing pure BFI instructions for bitfield insertion operations, unlike AArch64. The approach had to be a little different (in ISelDAGToDAG rather than ISelLowering), and the outcomes aren't identical but hopefully this gives it similar power. This should address PR19424. llvm-svn: 207102
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* ARM64: Combine shifts and uses from different basic block to bit-extract ↵Yi Jiang2014-04-211-3/+37
| | | | | | instruction llvm-svn: 206774
* ARM64: switch to IR-based atomic operations.Tim Northover2014-04-171-82/+0
| | | | | | | | Goodbye code! (Game: spot the bug fixed by the change). llvm-svn: 206490
* ARM64: add acquire/release versions of the existing atomic intrinsics.Tim Northover2014-04-171-3/+8
| | | | | | | These will be needed to support IR-level lowering of atomic operations. llvm-svn: 206489
* AArch64/ARM64: copy patterns for fixed-point conversionsTim Northover2014-04-151-0/+52
| | | | | | | | Code is mostly copied directly across, with a slight extension of the ISelDAGToDAG function so that it can cope with the floating-point constants being behind a litpool. llvm-svn: 206285
* ARM64: add support for AArch64's addsub_ext.llTim Northover2014-04-141-1/+1
| | | | | | | | | There was one definite issue in ARM64 (the off-by-1 check for whether a shift could be folded in) and one difference that is probably correct: ARM64 didn't fold nodes with multiple uses into the arithmetic operations unless optimising for code size. llvm-svn: 206168
* [ARM64,C++11]: Range'ify use-list iterators in DAGToDAG.Jim Grosbach2014-04-111-6/+3
| | | | llvm-svn: 206007
* ARM64: add 128-bit MLA operations to the custom selection code.Tim Northover2014-04-041-3/+9
| | | | | | | | | | | Without this change, the llvm_unreachable kicked in. The code pattern being spotted is rather non-canonical for 128-bit MLAs, but it can happen and there's no point in generating sub-optimal code for it just because it looks odd. Should fix PR19332. llvm-svn: 205615
* ARM64: convert fp16 narrowing ISel to pseudo-instructionTim Northover2014-04-021-13/+0
| | | | | | | | The previous attempt was fine with optimisations, but was actually rather cavalier with its types. When compiled at -O0, it produced invalid COPY MachineInstrs. llvm-svn: 205422
* ARM64: fix bug in ld3r (1d) SelectionDAG.Tim Northover2014-04-011-1/+1
| | | | llvm-svn: 205293
* ARM64: fix a couple of signed/unsigned comparison warnings.Tim Northover2014-03-311-2/+1
| | | | llvm-svn: 205174
* [ARM64] Fix 'assert("...")' to be 'assert(0 && "...")'. Otherwise, it isChandler Carruth2014-03-291-1/+1
| | | | | | | | | | | no assert at all. ;] Some of these should probably be switched to llvm_unreachable, but I didn't want to perturb the behavior in this patch. Found by -Wstring-conversion, which I'll try to turn on in CMake builds at least as it is finding useful things. llvm-svn: 205091
* ARM64: initial backend importTim Northover2014-03-291-0/+2395
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
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