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path: root/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
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* Avoid some 's' 16-bit instruction which partially update CPSRBob Wilson2011-04-191-85/+165
| | | | | | | (and add false dependency) when it isn't dependent on last CPSR defining instruction. rdar://8928208 llvm-svn: 129773
* Handle MI flags inside Thumb2SizeReduction pass.Anton Korobeynikov2011-03-051-0/+9
| | | | llvm-svn: 127102
* Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ↵Owen Anderson2011-02-081-43/+9
| | | | | | (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. llvm-svn: 125127
* Temporary workaround for a bad bug introduced by r121082 which replacedEvan Cheng2011-02-081-8/+5
| | | | | | | | | | | | t2LDRpci with t2LDRi12. There are a couple of problems with this. 1. The encoding for the literal and immediate constant are different. Note bit 7 of the literal case is 'U' so it can be negative. 2. t2LDRi12 is now narrowed to tLDRpci before constant island pass is run. So we end up never using the Thumb2 instruction, which ends up creating a lot more constant islands. llvm-svn: 125074
* The tLDR et al instructions were emitting either a reg/reg or reg/immBill Wendling2010-12-141-29/+36
| | | | | | | | | | | | | | | | instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. llvm-svn: 121747
* Refactor the ARM CMPz* patterns to just use the normal CMP instructions whenJim Grosbach2010-12-071-5/+3
| | | | | | | possible. They were duplicates for everything exception the source pattern before. llvm-svn: 121179
* Second attempt at converting Thumb2's LDRpci, including updating the ↵Owen Anderson2010-12-071-6/+42
| | | | | | gazillion places that need to know about it. llvm-svn: 121082
* The Thumb tADDrSPi instruction is not valid when the destination is SP.Bob Wilson2010-12-041-1/+8
| | | | | | Check for that and try narrowing it to tADDspi instead. Radar 8724703. llvm-svn: 120892
* Correctly size-reduce the t2CMPzrr instruction to tCMPzr when possible.Jim Grosbach2010-12-031-1/+13
| | | | | | | tCMPzhir has undefined behavior when both source registers are low registers. rdar://8728577 llvm-svn: 120858
* Reduce t2 ldr/str instructions to the correct t1 versions when there's anJim Grosbach2010-12-031-6/+6
| | | | | | immediate offset. llvm-svn: 120833
* Size reduction for tPUSH come from t2STMDB_UPD, not t2STMIA_UPD.Jim Grosbach2010-12-031-1/+2
| | | | llvm-svn: 120822
* Encode the multi-load/store instructions with their respective modes ('ia',Bill Wendling2010-11-161-19/+24
| | | | | | | | | 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
* Clarify commentJim Grosbach2010-09-141-2/+2
| | | | llvm-svn: 113846
* To shrink a t2LDM instruction to the 16-bit wide tLDM instruction, the baseJim Grosbach2010-09-071-0/+12
| | | | | | | | | | register must be one of the destination registers for the load. Otherwise, the tLDM instruction will write-back to the base register, which isn't what's desired (otherwise, we'd have a t2LDM_UPD instead). rdar://8394087 llvm-svn: 113297
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-1/+1
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* PR7458: Try commuting Thumb2 instruction operands to put them into 2-addressBob Wilson2010-06-241-3/+11
| | | | | | form so they can be narrowed to 16-bit instructions. llvm-svn: 106762
* fix typoJim Grosbach2010-06-081-1/+1
| | | | llvm-svn: 105634
* Use MachineBasicBlock::isLiveIn.Dan Gohman2010-04-131-8/+1
| | | | llvm-svn: 101144
* Fix another warning. There is a functionality change but I believe it's correct.Benjamin Kramer2010-03-131-2/+2
| | | | llvm-svn: 98430
* Change ARM ld/st multiple instructions to have variant instructions forBob Wilson2010-03-131-16/+35
| | | | | | | | | | | | | | | writebacks to the address register. This gets rid of the hack that the first register on the list was the magic writeback register operand. There was an implicit constraint that if that operand was not reg0 it had to match the base register operand. The post-RA scheduler's antidependency breaker did not understand that constraint and sometimes changed one without the other. This also fixes Radar 7495976 and should help the verifier work better for ARM code. There are now new ld/st instructions explicit writeback operands and explicit constraints that tie those registers together. llvm-svn: 98409
* Radar 7417921Jim Grosbach2010-02-091-1/+1
| | | | | | | | | | | tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to register instruction only works with low registers. Allowing high registers for the instruction resulted in the assembler choosing the wide (32-bit) encoding for the mov, but LLVM though the instruction was only 16 bits wide, so offset calculations for constant pools became incorrect, leading to out of range constant pool entries. llvm-svn: 95686
* Fix PR5694. The CMN instructions set the flags differently from CMP, so theyJim Grosbach2010-01-221-1/+2
| | | | | | | cannot be directly interchanged for comparisons against negated values. Disable the CMN instructions for the time being. llvm-svn: 94119
* improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner2009-12-031-1/+1
| | | | | | Patch by Howard Hinnant! llvm-svn: 90365
* Materialize global addresses via movt/movw pair, this is always betterAnton Korobeynikov2009-11-241-1/+7
| | | | | | | | | | | | | than doing the same via constpool: 1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2. 2. Load from constpool might stall up to 300 cycles due to cache miss. 3. Movt/movw does not use load/store unit. 4. Less constpool entries => better compiler performance. This is only enabled on ELF systems, since darwin does not have needed relocations (yet). llvm-svn: 89720
* Shrink ldr / str [sp, imm0-1024] to 16-bit instructions.Evan Cheng2009-11-191-8/+26
| | | | llvm-svn: 89326
* Remove includes of Support/Compiler.h that are no longer needed after theNick Lewycky2009-10-251-1/+0
| | | | | | VISIBILITY_HIDDEN removal. llvm-svn: 85043
* Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.Nick Lewycky2009-10-251-1/+1
| | | | | | | Chris claims we should never have visibility_hidden inside any .cpp file but that's still not true even after this commit. llvm-svn: 85042
* Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudoEvan Cheng2009-09-281-0/+1
| | | | | | | | | instruction. This makes it re-materializable. Thumb2 will split it back out into two instructions so IT pass will generate the right mask. Also, this expose opportunies to optimize the movw to a 16-bit move. llvm-svn: 82982
* Cast MO.getImm() to unsigned before comparing with an unsigned limit.Evan Cheng2009-09-091-1/+1
| | | | llvm-svn: 81318
* Remove some not-really-used variables, as warnedDuncan Sands2009-09-061-2/+0
| | | | | | about by icc (#593, partial). Patch by Erick Tryzelaar. llvm-svn: 81115
* remove various std::ostream version of printing methods fromChris Lattner2009-08-231-3/+4
| | | | | | | | MachineInstr and MachineOperand. This required eliminating a bunch of stuff that was using DOUT, I hope that bill doesn't mind me stealing his fun. ;-) llvm-svn: 79813
* Fix use after free in Thumb2SizeReduction (PR4707). A MachineInstr was used ↵Benjamin Kramer2009-08-161-1/+4
| | | | | | after erasure. llvm-svn: 79189
* Turn on if-conversion for thumb2.Evan Cheng2009-08-151-6/+14
| | | | llvm-svn: 79084
* Shrink ADR and LDR from constantpool late during constantpool island pass.Evan Cheng2009-08-141-0/+2
| | | | llvm-svn: 78970
* PredCC is meant to be 2 bits wide, like PredCC1.Evan Cheng2009-08-121-1/+1
| | | | llvm-svn: 78829
* Shrink Thumb2 movcc instructions.Evan Cheng2009-08-121-1/+2
| | | | llvm-svn: 78790
* Shrink ADDS, ADC, RSB, and SUBS.Evan Cheng2009-08-121-29/+103
| | | | llvm-svn: 78776
* Shrinkify Thumb2 r = add sp, imm.Evan Cheng2009-08-111-7/+18
| | | | llvm-svn: 78745
* Shrinkify Thumb2 load / store multiple instructions.Evan Cheng2009-08-111-34/+84
| | | | llvm-svn: 78717
* Fix the previous accidental commit. Now shrinking common Thumb2 load / store ↵Evan Cheng2009-08-111-2/+4
| | | | | | instructions. llvm-svn: 78659
* Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form toEvan Cheng2009-08-111-2/+140
| | | | | | | | | | match base only address, i.e. [r] since Thumb2 requires a offset register field. For those, use [r + imm12] where the immediate is zero. Note the generated assembly code does not look any different after the patch. But the bug would have broken the JIT (if there is Thumb2 support) and it can break later passes which expect the address mode to be well-formed. llvm-svn: 78658
* Watch out for empty BB.Evan Cheng2009-08-101-1/+1
| | | | llvm-svn: 78562
* rev, rev16, and revsh do not set CPSR.Evan Cheng2009-08-101-3/+3
| | | | llvm-svn: 78561
* Duh. Most 16-bit Thumb rr instructions are two-address. Fix table.Evan Cheng2009-08-101-9/+15
| | | | llvm-svn: 78560
* CPSR can be livein; transfer predicate operands correctly; tMUL is two-address.Evan Cheng2009-08-101-19/+57
| | | | llvm-svn: 78559
* Add support to reduce most of 32-bit Thumb2 arithmetic instructions.Evan Cheng2009-08-101-69/+147
| | | | llvm-svn: 78550
* Add support to convert 32-bit instructions to 16-bit non-two-address ones.Evan Cheng2009-08-091-35/+96
| | | | llvm-svn: 78540
* Add a skeleton Thumb2 instruction size reduction pass.Evan Cheng2009-08-081-0/+213
llvm-svn: 78456
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