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path: root/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
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* Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ↵Jakob Stoklund Olesen2012-08-281-21/+5
| | | | | | | | | | | ARM." This wasn't the right way to enforce ordering of atomics. We are already setting the isVolatile bit on memory operands of atomic operations which is good enough to enforce the correct ordering. llvm-svn: 162732
* Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.Jakob Stoklund Olesen2012-08-271-5/+21
| | | | | | | | | | | It is not safe to use normal LDR instructions because they may be reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag that prevents reordering. Atomic loads are also prevented from participating in rematerialization and load folding. llvm-svn: 162713
* Added missing CMN case in Thumb2SizeReduction pass so that LLVM emits ↵Sebastian Pop2012-05-041-0/+1
| | | | | | 16-bits encoding of CMN instructions. llvm-svn: 156195
* Tidy up. 80 columns.Jim Grosbach2012-04-061-1/+1
| | | | llvm-svn: 154226
* Use uint16_t to store registers and opcode in static tables in the target ↵Craig Topper2012-03-111-3/+3
| | | | | | specific backends. llvm-svn: 152537
* Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper2012-03-081-1/+1
| | | | llvm-svn: 152301
* Make sure the regs are low regs for tMUL size reduction.Jim Grosbach2012-02-241-1/+6
| | | | llvm-svn: 151318
* Thumb2 size reduction fix for tied operands of tMUL.Jim Grosbach2012-02-241-1/+13
| | | | | | | | | The tied source operand of tMUL is the second source operand, not the first like every other two-address thumb instruction. Special case it in the size reduction pass to make sure we create the tMUL instruction properly. llvm-svn: 151315
* Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.Evan Cheng2011-12-171-4/+7
| | | | llvm-svn: 146805
* - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng2011-12-141-13/+28
| | | | | | | | | | to finalize MI bundles (i.e. add BUNDLE instruction and computing register def and use lists of the BUNDLE instruction) and a pass to unpack bundles. - Teach more of MachineBasic and MachineInstr methods to be bundle aware. - Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to prevent IT blocks from being broken apart. llvm-svn: 146542
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-3/+2
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Avoid partial CPSR dependency from loop backedges. rdar://10357570Evan Cheng2011-10-271-24/+43
| | | | llvm-svn: 143145
* Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.Jim Grosbach2011-08-241-0/+1
| | | | | | | | | Add the predicate operand to the instructions. Update the back end accordingly where the instructions are used. Restrict the SP operands to actually only be SP, as otherwise these break assembly parsing for the normal instruction variants. llvm-svn: 138445
* ARM extend instructions simplification.Jim Grosbach2011-07-271-5/+13
| | | | | | | | Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-1/+1
| | | | | | ARM MC code from target. llvm-svn: 135636
* Fix off-by-one error.Jim Grosbach2011-07-011-1/+1
| | | | | | (low two bits always zero, so off by one bit of encoded value). llvm-svn: 134247
* Pseudo-ize t2MOVCC[ri].Jim Grosbach2011-07-011-2/+0
| | | | | | | | t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them. The Thumb1 versions, tMOVCC[ri] were only present for use by the size- reduction pass, so they're no longer necessary at all and can be deleted. llvm-svn: 134242
* Refact ARM Thumb1 tMOVr instruction family.Jim Grosbach2011-06-301-1/+1
| | | | | | | | | | Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions into tMOVr. There's no need to keep them separate. Giving the tMOVr instruction the proper GPR register class for its operands is sufficient to give the register allocator enough information to do the right thing directly. llvm-svn: 134204
* Size reducing SP adjusting t2ADDri needs to check predication.Jim Grosbach2011-06-301-1/+4
| | | | | | | tADDrSPi is not predicable, so we can't size-reduce a t2ADDri to it if the predicate is anything other than "always." llvm-svn: 134130
* Remove redundant Thumb2 ADD/SUB SP instruction definitions.Jim Grosbach2011-06-291-26/+47
| | | | | | | | | | Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the stack pointer. It can just use the normal add-register-immediate encoding since it can use all registers as a source, not just R0-R7. The extra instruction definitions are just duplicates of the normal instructions with the (not well enforced) constraint that the source register was SP. llvm-svn: 134114
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-34/+34
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* use the MachineInstrBuilder operator-> to simplify some code.Chris Lattner2011-04-291-1/+1
| | | | | | There are probably more instances of this floating around. llvm-svn: 130474
* Avoid some 's' 16-bit instruction which partially update CPSRBob Wilson2011-04-191-85/+165
| | | | | | | (and add false dependency) when it isn't dependent on last CPSR defining instruction. rdar://8928208 llvm-svn: 129773
* Handle MI flags inside Thumb2SizeReduction pass.Anton Korobeynikov2011-03-051-0/+9
| | | | llvm-svn: 127102
* Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ↵Owen Anderson2011-02-081-43/+9
| | | | | | (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. llvm-svn: 125127
* Temporary workaround for a bad bug introduced by r121082 which replacedEvan Cheng2011-02-081-8/+5
| | | | | | | | | | | | t2LDRpci with t2LDRi12. There are a couple of problems with this. 1. The encoding for the literal and immediate constant are different. Note bit 7 of the literal case is 'U' so it can be negative. 2. t2LDRi12 is now narrowed to tLDRpci before constant island pass is run. So we end up never using the Thumb2 instruction, which ends up creating a lot more constant islands. llvm-svn: 125074
* The tLDR et al instructions were emitting either a reg/reg or reg/immBill Wendling2010-12-141-29/+36
| | | | | | | | | | | | | | | | instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. llvm-svn: 121747
* Refactor the ARM CMPz* patterns to just use the normal CMP instructions whenJim Grosbach2010-12-071-5/+3
| | | | | | | possible. They were duplicates for everything exception the source pattern before. llvm-svn: 121179
* Second attempt at converting Thumb2's LDRpci, including updating the ↵Owen Anderson2010-12-071-6/+42
| | | | | | gazillion places that need to know about it. llvm-svn: 121082
* The Thumb tADDrSPi instruction is not valid when the destination is SP.Bob Wilson2010-12-041-1/+8
| | | | | | Check for that and try narrowing it to tADDspi instead. Radar 8724703. llvm-svn: 120892
* Correctly size-reduce the t2CMPzrr instruction to tCMPzr when possible.Jim Grosbach2010-12-031-1/+13
| | | | | | | tCMPzhir has undefined behavior when both source registers are low registers. rdar://8728577 llvm-svn: 120858
* Reduce t2 ldr/str instructions to the correct t1 versions when there's anJim Grosbach2010-12-031-6/+6
| | | | | | immediate offset. llvm-svn: 120833
* Size reduction for tPUSH come from t2STMDB_UPD, not t2STMIA_UPD.Jim Grosbach2010-12-031-1/+2
| | | | llvm-svn: 120822
* Encode the multi-load/store instructions with their respective modes ('ia',Bill Wendling2010-11-161-19/+24
| | | | | | | | | 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
* Clarify commentJim Grosbach2010-09-141-2/+2
| | | | llvm-svn: 113846
* To shrink a t2LDM instruction to the 16-bit wide tLDM instruction, the baseJim Grosbach2010-09-071-0/+12
| | | | | | | | | | register must be one of the destination registers for the load. Otherwise, the tLDM instruction will write-back to the base register, which isn't what's desired (otherwise, we'd have a t2LDM_UPD instead). rdar://8394087 llvm-svn: 113297
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-1/+1
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* PR7458: Try commuting Thumb2 instruction operands to put them into 2-addressBob Wilson2010-06-241-3/+11
| | | | | | form so they can be narrowed to 16-bit instructions. llvm-svn: 106762
* fix typoJim Grosbach2010-06-081-1/+1
| | | | llvm-svn: 105634
* Use MachineBasicBlock::isLiveIn.Dan Gohman2010-04-131-8/+1
| | | | llvm-svn: 101144
* Fix another warning. There is a functionality change but I believe it's correct.Benjamin Kramer2010-03-131-2/+2
| | | | llvm-svn: 98430
* Change ARM ld/st multiple instructions to have variant instructions forBob Wilson2010-03-131-16/+35
| | | | | | | | | | | | | | | writebacks to the address register. This gets rid of the hack that the first register on the list was the magic writeback register operand. There was an implicit constraint that if that operand was not reg0 it had to match the base register operand. The post-RA scheduler's antidependency breaker did not understand that constraint and sometimes changed one without the other. This also fixes Radar 7495976 and should help the verifier work better for ARM code. There are now new ld/st instructions explicit writeback operands and explicit constraints that tie those registers together. llvm-svn: 98409
* Radar 7417921Jim Grosbach2010-02-091-1/+1
| | | | | | | | | | | tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to register instruction only works with low registers. Allowing high registers for the instruction resulted in the assembler choosing the wide (32-bit) encoding for the mov, but LLVM though the instruction was only 16 bits wide, so offset calculations for constant pools became incorrect, leading to out of range constant pool entries. llvm-svn: 95686
* Fix PR5694. The CMN instructions set the flags differently from CMP, so theyJim Grosbach2010-01-221-1/+2
| | | | | | | cannot be directly interchanged for comparisons against negated values. Disable the CMN instructions for the time being. llvm-svn: 94119
* improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner2009-12-031-1/+1
| | | | | | Patch by Howard Hinnant! llvm-svn: 90365
* Materialize global addresses via movt/movw pair, this is always betterAnton Korobeynikov2009-11-241-1/+7
| | | | | | | | | | | | | than doing the same via constpool: 1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2. 2. Load from constpool might stall up to 300 cycles due to cache miss. 3. Movt/movw does not use load/store unit. 4. Less constpool entries => better compiler performance. This is only enabled on ELF systems, since darwin does not have needed relocations (yet). llvm-svn: 89720
* Shrink ldr / str [sp, imm0-1024] to 16-bit instructions.Evan Cheng2009-11-191-8/+26
| | | | llvm-svn: 89326
* Remove includes of Support/Compiler.h that are no longer needed after theNick Lewycky2009-10-251-1/+0
| | | | | | VISIBILITY_HIDDEN removal. llvm-svn: 85043
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